Abstract: Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.

Abstract: A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.

Abstract: A new class traces for a processing engine, called “extended blocks,” possess an architecture that permits possible many entry points but only a single exit point. These extended blocks may be indexed based upon the address of the last instruction therein. Use of the new trace architecture provides several advantages, including reduction of instruction redundancies, dynamic block extension and a sharing of instructions among various extended blocks.

Abstract: A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.

Abstract: A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

Abstract: The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a microprocessor and a chipset coupled to the microprocessor. The microprocessor removes stale branch instructions prior to the execution of a first cache line by finding existing branch prediction data for the first cache line.

Abstract: An electronic device including a predictor that has a collision history table (CHT) is presented. An extended load buffer is connected to the predictor. Also included is a marking unit, a comparing unit and a recovery unit connected to the extended load buffer. Unexecuted load instructions are advanced over store instructions. Also presented is a method for fetching an instruction and determining if an instruction is a store or a load. If the instruction is a store, then the method performs a silent store prediction. If the instruction is a load, a predicted silent store instruction is bypassed and the load instruction is executed.

Abstract: Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.

Abstract: A method for renaming a source for use with a processor, the method including providing an instruction, building instruction dependency information based on the instruction, caching the instruction based on the instruction dependency information to provide a cached instruction, renaming a register based on the cached instruction to provide a renamed register, and multiplexing the instruction dependency information and the renamed register to rename the source.

Abstract: A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a microprocessor and a chipset coupled to the microprocessor. The microprocessor removes stale branch instructions prior to the execution of a first cache line by finding existing branch prediction data for the first cache line.

Abstract: A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

Abstract: According to one embodiment, a method features operations for executing instructions in an instruction window. The first and second instructions are examined to determine their sources and destinations. The written on bit of the first instruction is set to a “written on” state if the destinations of the first and second instructions are the same while a used bit of the first instruction is set to a “used” state if the source of the second instruction is the destination of the first instruction. Thereafter, a priority of the first instruction can be determined from the written on and used bits.

Abstract: Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.

Abstract: A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

Abstract: A system and method for recovering from mispredicted paths in pipelined computer architectures. Targets within an instruction window exhibit spatial locality. To exploit this property, a mechanism detects the branch target within the instruction window. A second process eliminates the need for full renaming and re-execution of mispredicted paths by handling a dependency chain of instructions.

Abstract: Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.

Abstract: The present invention is directed to a computer system and method for early resolution of a set of critical instructions. The computer system may include a scoreboard, a scheduling window and a confidence predictor. The scoreboard may include a set of reservation stations. Each one of the set of reservation stations may correspond to one of a set of decoded instructions. Each one of the set of reservation stations may have a priority field. The scheduling window may maintain the scoreboard, wherein if one of the set of decoded instructions is one of the set of critical instructions, the scheduling window may mark the priority field corresponding to the particular one of the set of decoded instructions and also may find and mark the priority field of each of a set of base instructions upon which the particular one of the set of decoded instructions depends. The confidence predictor may also be used to predict whether one of the set of decoded instructions is one of the set of critical instructions.

Abstract: A cache bank prediction unit is provided for use in a processor having a plurality of cache memory banks. The cache bank prediction unit has an input port that receives an instruction. The cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of cache banks is associated with the instruction.