Patents by Inventor Adimulam Ramesh Babu

Adimulam Ramesh Babu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978151
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a BVH structure including a plurality of nodes, wherein the BVH structure is associated with geometry data for a plurality of primitives in a scene, wherein each of the plurality of nodes is associated with one or more primitives, where a first level BVH includes a set of first nodes and a second level BVH includes a set of second nodes. The apparatus may also allocate information for a plurality of second nodes in the set of second nodes to at least one first node in the set of first nodes. Further, the apparatus may store the allocated information for the plurality of second nodes in the set of second nodes in the at least one first node in the set of first nodes.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: May 7, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Adimulam Ramesh Babu, Srihari Babu Alla, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar
  • Publication number: 20240070964
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a BVH structure including a plurality of nodes, wherein the BVH structure is associated with geometry data for a plurality of primitives in a scene, wherein each of the plurality of nodes is associated with one or more primitives, where a first level BVH includes a set of first nodes and a second level BVH includes a set of second nodes. The apparatus may also allocate information for a plurality of second nodes in the set of second nodes to at least one first node in the set of first nodes. Further, the apparatus may store the allocated information for the plurality of second nodes in the set of second nodes in the at least one first node in the set of first nodes.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Adimulam RAMESH BABU, Srihari Babu ALLA, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR
  • Patent number: 11893677
    Abstract: Systems and techniques are provided for widening a hierarchical structure for ray tracing. For instance, a process can include obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure and determining one or more candidate hierarchical acceleration data structures each including the plurality of primitives. A cost metric can be determined for the one or more candidate hierarchical acceleration data structures and, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures can be determined. An output hierarchical acceleration data structure can be generated based on the compressibility prediction.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: February 6, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Adimulam Ramesh Babu, Srihari Babu Alla, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar, David Kirk McAllister
  • Publication number: 20240037840
    Abstract: Systems and techniques are provided for widening a hierarchical structure for ray tracing. For instance, a process can include obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure and determining one or more candidate hierarchical acceleration data structures each including the plurality of primitives. A cost metric can be determined for the one or more candidate hierarchical acceleration data structures and, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures can be determined. An output hierarchical acceleration data structure can be generated based on the compressibility prediction.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Adimulam RAMESH BABU, Srihari Babu ALLA, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR, David Kirk MCALLISTER
  • Publication number: 20230252685
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU or CPU. The apparatus may allocate each of a plurality of primitives in a scene into one of a plurality of bounding boxes, each of the plurality of bounding boxes corresponding to a plurality of nodes including internal nodes and leaf nodes. The apparatus may also identify whether each of the plurality of nodes is one of the internal nodes or one of the leaf nodes. Further, the apparatus may estimate a compressibility of each of the plurality of nodes if the node is one of the leaf nodes, the compressibility of the node corresponding to whether the node is compressible. The apparatus may also compress data corresponding to each of the plurality of nodes if the node is estimated to be compressible.
    Type: Application
    Filed: February 4, 2022
    Publication date: August 10, 2023
    Inventors: Adimulam RAMESH BABU, Srihari Babu ALLA, David Kirk MCALLISTER
  • Patent number: 11593990
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a BVH structure including a plurality of levels and a plurality of nodes, the BVH structure being associated with geometry data for a plurality of primitives in a scene. The apparatus may also identify an amount of storage in a GMEM that is available for storing at least some of the plurality of nodes in the BVH structure. Further, the apparatus may allocate the BVH structure into a first BVH section including a plurality of first nodes and a second BVH section including a plurality of second nodes. The apparatus may also store first data associated with the plurality of first nodes in the GMEM and second data associated with the plurality of first nodes and the plurality of second nodes in a system memory.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: February 28, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Adimulam Ramesh Babu, Srihari Babu Alla, David Kirk McAllister
  • Patent number: 11176734
    Abstract: The present disclosure relates to methods and apparatus for graphics processing. An example method generally includes receiving, at a graphics processing unit (GPU), a plurality of commands corresponding to a plurality of draws across a frame, each of the plurality of commands indicating a depth test direction with respect to a low-resolution depth (LRZ) buffer for the corresponding draw. The method generally includes maintaining, at the GPU, a LRZ status buffer to store a corresponding depth test direction for a first command in time of the plurality of commands processed by the GPU. The method generally includes disabling, at the GPU, use of the LRZ buffer for depth testing for any of the plurality of commands remaining unprocessed after processing a command of the plurality of commands having a different depth test direction than the corresponding depth test direction stored in the LRZ status buffer.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: November 16, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Srihari Babu Alla, Adimulam Ramesh Babu, Jonnala Gadda Nagendra Kumar, Avinash Seetharamaiah, Tao Wang, Xuefeng Tang, Thomas Edwin Frisinger, Andrew Evan Gruber