Patents by Inventor Aditya Bhuvanagiri
Aditya Bhuvanagiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9591254Abstract: An apparatus configured to record and process video information includes a memory, display, and a processor in communication with the memory and the display. The memory is configured to store video data. The display is configured to display a preview of the video data. The processor is configured to record the video data at a first frame rate, process the recorded video data via removing one or more frames from the recorded video data, the processed video data having a second frame rate that is lower than the first frame rate, and generate the preview to be displayed by the display based at least in part on the processed video data.Type: GrantFiled: March 26, 2015Date of Patent: March 7, 2017Assignee: QUALCOMM IncorporatedInventors: Aditya Bhuvanagiri, R. V. Jagannadha Rao Doddi, Ajit Deepak Gupte, Ashish Bajaj, Rajeshwar Kurapaty, Aravind Korlepara
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Publication number: 20160286155Abstract: An apparatus configured to record and process video information includes a memory, display, and a processor in communication with the memory and the display. The memory is configured to store video data. The display is configured to display a preview of the video data. The processor is configured to record the video data at a first frame rate, process the recorded video data via removing one or more frames from the recorded video data, the processed video data having a second frame rate that is lower than the first frame rate, and generate the preview to be displayed by the display based at least in part on the processed video data.Type: ApplicationFiled: March 26, 2015Publication date: September 29, 2016Inventors: Aditya BHUVANAGIRI, R.V.Jagannadha Rao DODDI, Ajit Deepak GUPTE, Ashish BAJAJ, Rajeshwar KURAPATY, Aravind KORLEPARA
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Publication number: 20150103909Abstract: The techniques of this disclosure relate to video encoding and include using an inter mode determination for neighboring blocks, rather than the final prediction mode determination for the neighboring block, when determining an inter mode for a current block. In this way, inter mode and intra mode estimation may be separated and performed in different stages of a multi-threaded parallel video encoding implementation. In addition, this disclosure also proposes generating sub-pixel values in a third stage of the multi-threaded parallel video encoding implementation at a frame level, rather than for each macroblock during inter mode estimation process for that macroblock.Type: ApplicationFiled: July 2, 2014Publication date: April 16, 2015Inventors: Umesh Kumar Pandey, Xinping Zhang, Aditya Bhuvanagiri, Kim-Chyan Gan, Santhosh Kumar Gunna, Adithya Prakash, Aravind Korlepara, Jayant Ingale, Arjun Sitaram, Revathy Shunmugam
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Patent number: 8792550Abstract: This disclosure relates to techniques for preventing or reducing the appearance of undesirable color and/or gray patches in decoded video sequences due to generation of out-of-bound quantized transform coefficients during video encoding. Insufficient compression of a video block according to a selected encoding mode and a selected quantization parameter (QP) value may result in the generation and subsequent clipping of out-of-bound quantized transform coefficients for a given video coding standard. The techniques include predicting whether out-of-bound quantized transform coefficients will be generated for a video block, and adjusting at least one of the selected encoding mode and the selected QP value for the video block to prevent the generation of out-of-bound quantized transform coefficients.Type: GrantFiled: August 4, 2011Date of Patent: July 29, 2014Assignee: QUALCOMM IncorporatedInventors: Venkata Naga Poleswara Rao Karuchula, Ashish Bajaj, Surya Manikya Phanindra Kalanadhabhatla, Praneeth Paladugu, Aditya Bhuvanagiri
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Patent number: 8780978Abstract: A video encoder may reduce bandwidth consumption by skipping encoding of or reducing an encoding rate of video frames corresponding to silent audio frames, that is, audio frames that do not include speech data. In one example, an apparatus includes a video encoder comprising a coding unit configured to encode video data in a first or second mode and a mode select unit configured to receive an indication of whether encoded audio data corresponding to the video data to be encoded includes speech data. When the audio data includes speech data, the mode select unit selects the first mode, and when the audio data does not include speech data, the mode select unit selects the second mode. The second mode consumes relatively less bandwidth, e.g., by reducing a bitrate, modifying a quantization parameter to increase quantization, and/or reducing a frame rate relative to the first mode.Type: GrantFiled: November 4, 2009Date of Patent: July 15, 2014Assignee: QUALCOMM IncorporatedInventors: Chandra Mouli Polisetty, Aditya Bhuvanagiri
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Publication number: 20130034149Abstract: This disclosure relates to techniques for preventing or reducing the appearance of undesirable color and/or gray patches in decoded video sequences due to generation of out-of-bound quantized transform coefficients during video encoding. Insufficient compression of a video block according to a selected encoding mode and a selected quantization parameter (QP) value may result in the generation and subsequent clipping of out-of-bound quantized transform coefficients for a given video coding standard. The techniques include predicting whether out-of-bound quantized transform coefficients will be generated for a video block, and adjusting at least one of the selected encoding mode and the selected QP value for the video block to prevent the generation of out-of-bound quantized transform coefficients.Type: ApplicationFiled: August 4, 2011Publication date: February 7, 2013Applicant: QUALCOMM IncorporatedInventors: Venkata Naga Poleswara Rao Karuchula, Ashish Bajaj, Surya Manikya Phanindra Kalanadhabhatla, Praneeth Paladugu, Aditya Bhuvanagiri
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Publication number: 20110103468Abstract: A video encoder may reduce bandwidth consumption by skipping encoding of or reducing an encoding rate of video frames corresponding to silent audio frames, that is, audio frames that do not include speech data. In one example, an apparatus includes a video encoder comprising a coding unit configured to encode video data in a first or second mode and a mode select unit configured to receive an indication of whether encoded audio data corresponding to the video data to be encoded includes speech data. When the audio data includes speech data, the mode select unit selects the first mode, and when the audio data does not include speech data, the mode select unit selects the second mode. The second mode consumes relatively less bandwidth, e.g., by reducing a bitrate, modifying a quantization parameter to increase quantization, and/or reducing a frame rate relative to the first mode.Type: ApplicationFiled: November 4, 2009Publication date: May 5, 2011Applicant: Qualcomm IncorporatedInventors: Chandra Mouli Polisetty, Aditya Bhuvanagiri
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Patent number: 7917569Abstract: A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for geneType: GrantFiled: October 20, 2005Date of Patent: March 29, 2011Assignee: STMicroelectronics Pvt. Ltd.Inventors: Aditya Bhuvanagiri, Rakesh Malik, Nitin Chawla
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Patent number: 7698355Abstract: A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.Type: GrantFiled: August 29, 2005Date of Patent: April 13, 2010Assignee: STMicroelectronics Pvt. Ltd.Inventors: Aditya Bhuvanagiri, Harvinder Singh, Rakesh Malik, Nitin Chawla
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Publication number: 20060153321Abstract: A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for geneType: ApplicationFiled: October 20, 2005Publication date: July 13, 2006Applicant: STMicroelectronics Pvt.Ltd.Inventors: Aditya Bhuvanagiri, Rakesh Malik, Nitin Chawla
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Publication number: 20060120494Abstract: A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.Type: ApplicationFiled: August 29, 2005Publication date: June 8, 2006Applicant: STMicroelectronics Pvt. Ltd.Inventors: Aditya Bhuvanagiri, Harvinder Singh, Rakesh Malik, Nitin Chawla