Abstract: In an embodiment, a system includes a graphics processing unit (GPU) that includes one or more GPU engines, and a microcontroller. The microcontroller is to assign a respective schedule slot for each of a plurality of virtual machines (VMs). When a particular VM is scheduled to access a first GPU engine, the particular VM has exclusive access to the first GPU engine. Other embodiments are described and claimed.

Abstract: Memory-based semaphores are described that are useful for synchronizing processes between different processing engines. In one example, operations include executing a first process at a first processing engine, the executing including updating a memory register, sending a signal from the first processing engine to a second processing engine that the memory register has been updated, the signal including a memory register address to identify the updated memory register inline data and a dataword, fetching data from the memory register by the second processing engine, comparing the fetched data to the received dataword, and conditionally executing a next command of a second process at the second processing engine based on the comparison.

Abstract: An apparatus and method are described for fine grained sharing of graphics processing resources for example, one embodiment of a graphics processing apparatus comprises: a plurality of command buffers to store work elements from a plurality of virtual machines or applications, each work element indicating a command to be processed by graphics hardware and data identifying the virtual machine or application which generated the work element; a plurality of doorbell registers or memory regions, each doorbell register or memory region associated with a particular virtual machine or application, a virtual machine or application to store an indication in its doorbell register or memory region when it has stored a work element to a command buffer; and a work scheduler to read a work element from a command buffer responsive to detecting an indication in a doorbell register, the work scheduler to combine work elements from multiple virtual machines or applications in a submission to a graphics engine, the graphics eng

Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a register file having a plurality of channels to store data and an execution unit to examine data at each of the plurality of channels, read a data value from a first of the plurality of channels upon a determination that each of the plurality of channels has the same data and execute a single input multi data (SIMD) instruction based on the data value.

Abstract: Methods and apparatus relating to mid-thread pre-emption with software assisted context switch are described. In an embodiment, one or more threads executing on a Graphics Processing Unit (GPU) are stopped at an instruction level granularity in response to a request to pre-empt the one or more threads. The context data of the one or more threads is copied to memory in response to completion of the one or more threads at the instruction level granularity and/or one or more instructions. Other embodiments are also disclosed and claimed.

Abstract: Systems and methods may provide for receiving a plurality of signals from a software module associated with a shared resource such as, for example, an unordered access view (UAV). The plurality of signals may include a first signal that indicates whether a draw call accesses the shared resource, a second signal that indicates whether a boundary of the draw call has been reached, and a third signal that indicates whether the draw call has a coherency requirement. Additionally, a workload corresponding to the draw call may be selectively dispatched in a shader invocation based on the plurality of signals.

Abstract: Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

Abstract: Described herein are technologies related to a ensuring that graphics commands and graphics context are offloading and scheduled for consumption as the commands and graphics context are sent from coherent to non-coherent memory/fabric in a “processor to processor” handoff or transaction.

Abstract: Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged.

Abstract: Described herein are computer graphics technologies to facilitate effective and efficient memory handling for blocks of memory including texture maps. More particularly, one or more implementations described herein facilitates hierarchical lossless compression of memory with null data support for memory resources, including texture maps. More particularly still, one or more implementations described herein facilitates the use of meta-data for lossless compression and the support of null encodings for Tiled Resources. This technology also permits use of the fast-clear compression method, where meta-data specifies that the entire access should return some specified clear value.

Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

Abstract: An electronic device is described herein. The electronic device may include a page walker module to receive a page request of a graphics processing unit (GPU). The page walker module may detect a page fault associated with the page request. The electronic device may include a controller, at least partially comprising hardware logic. The controller is to monitor execution of the page request having the page fault. The controller determines whether to suspend execution of a work item at the GPU associated with the page request having the page fault, or to continue execution of the work item based on factors associated with the page request.

Abstract: An apparatus and method for identifying sub-groups of execution resources for parallel pixel processing. For example, one embodiment of a method comprises: determining X and Y coordinates for a pixel block to be processed; performing a first set of one or more modulus operations using even bits from the X and Y coordinates to generate a first intermediate result; performing a second set of one or more modulus operations using odd bits from the X and Y coordinates to generate a second intermediate result; comparing the first intermediate result and the second intermediate result to generate a final result; and using the final result to select a first set of processing resources from a set of N processing resources for processing the pixel block.

Abstract: Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.

Abstract: Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.

Abstract: Mid-command buffer preemption is described for graphics workloads in a graphics processing environment. In one example, instructions of a first context are executed at a graphics processor, the first context has a sequence of instructions in an addressable buffer and at least one of the instructions is a preemption instruction. Upon executing the preemption instruction, execution of the first context is stopped before the sequence of instructions is completed. An address is stored for an instruction with which the first context will be resumed. The second context is executed, and upon completion of the execution of the second context, the execution of the first context is resumed at the stored address.

Abstract: Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user-mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged. A graphics processing unit (GPU) can receive the privilege-designated batch buffers from the KMD, and is configured to disallow execution of any privileged command from a non-privileged batch buffer, while any privileged commands from privileged batch buffers are unrestricted by the GPU.

Abstract: Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.

Abstract: Methods and systems may provide for storing a set of post-synchronization operations to a graphics memory and sending a flush marker to a graphics pipeline. Additionally, the set of post-synchronization operations may be processed in response to the flush marker exiting the graphics pipeline. In one example, the set of post-synchronization operations includes one or more atomic operations. Moreover, the set of post-synchronization operations may be obtained from an inline portion of an atomics command.

Abstract: Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.