Patents by Inventor Aditya Nellutla

Aditya Nellutla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240070975
    Abstract: Embodiments are disclosed for blending complex objects. The method may include identifying a first complex object and a second complex object. A first primary object associated with the first complex object and a first sequence of geometric repeat operations are determined. A second primary object associated with the second complex object and second sequence of geometric repeat operations are also determined. A blending operation is applied to the first primary object and the second primary object to generate one or more intermediate primary objects. One or more intermediate complex objects are generated from the one or more intermediate primary objects.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: Adobe Inc.
    Inventors: Aditya NELLUTLA, Apurva KUMAR
  • Publication number: 20240070891
    Abstract: Embodiments are disclosed for identifying and generating symmetrical repeat edits to similar objects in an image. A selection of a first object and an edit to the first object in an image is received. The image is searched for a plurality of candidate objects that have a similar shape to the first object and the plurality of candidate objects are filtered to include one or more objects that are symmetrical with the first object. A symmetric object is selected from the plurality of candidate objects. An axis of symmetry is computed between the symmetric object and the first object. The edit is applied to the symmetric object and to the first object.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: Adobe Inc.
    Inventors: Aditya NELLUTLA, Harish KUMAR
  • Patent number: 10409359
    Abstract: Generally, the described techniques provide for dividing a frame into bins and grouping the bins according to load information associated with the bins. For example, a device may divide a frame into a plurality of bins. The device may determine load information for each bin of the plurality of bins and order the plurality of bins, based on the load information for each bin, in a plurality of bin groups each associated with a power mode of the device. The device may then execute one or more rendering commands for each bin group of the plurality of groups at the power mode associated with the each bin group. By providing for bin-level granularity in power-mode allocation, the described techniques may improve rendering performance.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Aditya Nellutla
  • Publication number: 20190221009
    Abstract: Generally, the described techniques provide for dividing a frame into bins and grouping the bins according to load information associated with the bins. For example, a device may divide a frame into a plurality of bins. The device may determine load information for each bin of the plurality of bins and order the plurality of bins, based on the load information for each bin, in a plurality of bin groups each associated with a power mode of the device. The device may then execute one or more rendering commands for each bin group of the plurality of groups at the power mode associated with the each bin group. By providing for bin-level granularity in power-mode allocation, the described techniques may improve rendering performance.
    Type: Application
    Filed: January 17, 2018
    Publication date: July 18, 2019
    Inventor: Aditya Nellutla
  • Publication number: 20190220411
    Abstract: Generally, the described techniques provide for efficiently partitioning a frame into bins. For example, a device may identify a size of a cache and determine dimensions of a frame. The device may divide the frame into a first region and a second region that is separate from the first region. The device may then divide the first region into a plurality of bins that have a first vertical dimension and a first horizontal dimension (or varying vertical and/or horizontal dimensions) and divide the second region into one or more bins, where at least one bin has a second vertical dimension that is greater than the first vertical dimension or a second horizontal dimension that is greater than the first horizontal dimension. The device may render the frame using the plurality of bins and the one or more bins. By efficiently partitioning the frame, rendering performance may be improved.
    Type: Application
    Filed: January 17, 2018
    Publication date: July 18, 2019
    Inventors: Aditya Nellutla, Anoop Kumar Yerukala