Abstract: A system includes a plurality of digital-to-analog converter (DAC) channels. Each DAC channel includes a current control circuit which receives a start limit signal or an end limit signal. The current control circuit reduces an output current limit of the channel responsive to the start limit signal and increases the output current limit responsive to the end limit signal. Each channel includes a current sensor circuit adapted to measure the output current of the channel and provide a channel over-current alert signal if the output current rises above a high current limit. The system includes a controller which asserts the start limit signal if the number of channels exceeding the high current limit is greater than a maximum allowable number and asserts the end limit signal if the number of channels exceeding the high current limit is less than the maximum allowable number minus a hysteresis value.

Abstract: A system includes a plurality of digital-to-analog converter (DAC) channels. Each DAC channel includes a current control circuit which receives a start limit signal or an end limit signal. The current control circuit reduces an output current limit of the channel responsive to the start limit signal and increases the output current limit responsive to the end limit signal. Each channel includes a current sensor circuit adapted to measure the output current of the channel and provide a channel over-current alert signal if the output current rises above a high current limit. The system includes a controller which asserts the start limit signal if the number of channels exceeding the high current limit is greater than a maximum allowable number and asserts the end limit signal if the number of channels exceeding the high current limit is less than the maximum allowable number minus a hysteresis value.

Abstract: A circuit includes a first transistor having a first control input and first and second current terminals, and a second transistor having a second control input and third and fourth current terminals. A third transistor has a third control input and fifth and sixth current terminals, the fifth current terminal coupled to the first current terminal at a first supply voltage node. A fourth transistor has a fourth control input and seventh and eighth current terminals, the seventh current terminal coupled to the second and sixth current terminals. A pulse generator has a pulse generator input and a first pulse generator output, the pulse generator input configured to receive a switch control signal, and the first pulse generator output coupled to the first control input. The third control input is configured to receive either the switch control signal or a logical inverse of the switch control signal.