Patents by Inventor Adriaan van de Ven

Adriaan van de Ven has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11683310
    Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: June 20, 2023
    Assignee: Intel Corporation
    Inventors: Barry E. Huntley, Gilbert Neiger, H. Peter Anvin, Asit K. Mallick, Adriaan Van De Ven, Scott D. Rodgers
  • Publication number: 20210258311
    Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.
    Type: Application
    Filed: May 4, 2021
    Publication date: August 19, 2021
    Applicant: Intel Corporation
    Inventors: Barry E. HUNTLEY, Gilbert NEIGER, H. Peter ANVIN, Asit K. MALLICK, Adriaan VAN DE VEN, Scott D. RODGERS
  • Patent number: 11019061
    Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Barry E. Huntley, Gilbert Neiger, H. Peter Anvin, Asit K. Mallick, Adriaan Van De Ven, Scott D. Rodgers
  • Patent number: 10999284
    Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Barry E. Huntley, Gilbert Neiger, H. Peter Anvin, Asit K. Mallick, Adriaan Van De Ven, Scott D. Rodgers
  • Publication number: 20210051149
    Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 18, 2021
    Applicant: Intel Corporation
    Inventors: Barry E. HUNTLEY, Gilbert NEIGER, H. Peter ANVIN, Asit K. MALLICK, Adriaan VAN DE VEN, Scott D. RODGERS
  • Patent number: 10445009
    Abstract: Systems and methods that manage memory usage by a virtual machine are provided. These systems and methods compact the virtual machine's memory footprint, thereby promoting efficient use of memory and gaining performance benefits of increased data locality. In some embodiments, a guest operating system running within the virtual machine is enhanced to allocate its VM memory in a compact manner. The guest operating system includes a memory manager that is configured to reference an artificial access cost when identifying memory areas to allocate for use by applications. These access costs are described as being artificial because they are not representative of actual, hardware based access costs, but instead are fictitious costs that increase as the addresses of the memory areas increase. Because of these increasing artificial access costs, the memory manager identifies memory areas with lower addresses for allocation and use prior to memory areas with higher addresses.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 15, 2019
    Assignee: INTEL CORPORATION
    Inventors: Graham Whaley, Adriaan van de Ven, Manohar R. Castelino, Jose C. Venegas Munoz, Samuel Ortiz
  • Patent number: 10241821
    Abstract: The present disclosure provides RNG states. Generating the RNG states can include creating a first VM with a first RNG state and a second VM with a second RNG state and generating a plurality of interrupts for the first VM and the second VM. Generating the RNG states can also include providing the plurality of interrupts to the first VM with a first plurality of time intervals between the plurality of interrupts to configure the first RNG state and providing the plurality of interrupts to the second VM with a second plurality of time intervals, between the plurality of interrupts, that are different from the first plurality of time intervals to configure the second RNG state to be different from the first RNG state.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: March 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Josh Triplett, Adriaan Van De Ven
  • Publication number: 20190089709
    Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Inventors: Barry E. HUNTLEY, Gilbert NEIGER, H. Peter ANVIN, Asit K. MALLICK, Adriaan VAN DE VEN, Scott D. RODGERS
  • Publication number: 20190004720
    Abstract: Systems and methods that manage memory usage by a virtual machine are provided. These systems and methods compact the virtual machine's memory footprint, thereby promoting efficient use of memory and gaining performance benefits of increased data locality. In some embodiments, a guest operating system running within the virtual machine is enhanced to allocate its VM memory in a compact manner. The guest operating system includes a memory manager that is configured to reference an artificial access cost when identifying memory areas to allocate for use by applications. These access costs are described as being artificial because they are not representative of actual, hardware based access costs, but instead are fictitious costs that increase as the addresses of the memory areas increase. Because of these increasing artificial access costs, the memory manager identifies memory areas with lower addresses for allocation and use prior to memory areas with higher addresses.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventors: Graham Whaley, Adriaan van de Ven, Manohar R. Castelino, Jose C. Venegas Munoz, Samuel Ortiz
  • Patent number: 10135825
    Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Barry E. Huntley, Gilbert Neiger, H. Peter Anvin, Asit K. Mallick, Adriaan Van De Ven, Scott D. Rodgers
  • Patent number: 10073703
    Abstract: In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the OS boot process, and optimizing the list of files to generate an optimized file list for use in future OS boot processes, where the optimizing is according to a first optimization technique if the files were accessed from a solid state medium and according to a second optimization technique if the files were accessed from a rotating medium. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventor: Adriaan Van De Ven
  • Patent number: 10027695
    Abstract: Technologies are provided in embodiments to detect malware. Embodiments are to receive context information related to a potentially affected system, create a prediction of normal traffic based, at least in part, on the received context information, compare network traffic associated with the potentially affected system to the prediction of normal traffic, and take an action based, at least in part, on the comparison. The action may be taken if the network traffic is not within an acceptable deviation range of the prediction of normal traffic or the action may be taken based on a degree of deviation of the network traffic from the prediction of normal traffic. The acceptable deviation range and the degree of deviation are based, at least in part, on a type of network traffic. The acceptable deviation range and the degree of deviation are based, at least in part, on a volume of network traffic.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Dirk Hohndel, Adriaan van de Ven
  • Publication number: 20180157510
    Abstract: The present disclosure provides RNG states. Generating the RNG states can include creating a first VM with a first RNG state and a second VM with a second RNG state and generating a plurality of interrupts for the first VM and the second VM.
    Type: Application
    Filed: December 2, 2016
    Publication date: June 7, 2018
    Applicant: INTEL CORPORATION
    Inventors: Josh TRIPLETT, Adriaan VAN DE VEN
  • Patent number: 9942839
    Abstract: Technologies for reducing connection time to a wireless access point includes recording wireless connection information in a log, computing parameters as a function of past wireless connection information in the log, generating an ordered list of wireless access points most likely to be available for reconnection at a desired time as a function of recent wireless connection information in the log, and directly probing a wireless access point instead of initiating a wireless access point scan. In some embodiments, computing parameters as a function of past wireless connection information in the log comprises performing genetic programming operations to generate prediction programs for later prediction of wireless access points most likely to be available for reconnection at a desired time.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Adriaan van de Ven, James T. Kukunas
  • Patent number: 9886667
    Abstract: Embodiments of techniques and systems for performance of predicted actions are described. In embodiments, a predicted action performance engine (“PAE”) may receive one or probabilities of potential actions that may be performed on a computing device. The PAE may also receive a system context for the computing device describing available resources on the computing device, workload, etc. Based on these probabilities and the system context, the PAE may determine one or more predicted actions and/or resource utilizations which are likely to occur and which may be performed ahead of time. The PAE may then facilitate performance of these actions and/or resource utilizations. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: February 6, 2018
    Assignee: Intel Corporation
    Inventors: Dirk Hohndel, Adriaan Van De Ven
  • Patent number: 9864702
    Abstract: Techniques to prelink software to improve memory de-duplication in a virtual system are described. An apparatus may comprise a processor circuit, a memory unit coupled to the processor circuit to store private memory pages for multiple virtual machines, and a dynamic linker application operative on the processor circuit to link a binary version of a software program with associated program modules at run-time of the binary version on a virtual machine. The dynamic linker application may comprise a master prelink component operative on the processor circuit to relocate a first set of program modules for a first binary version of the software program for a first virtual machine using a first set of virtual memory addresses from a first private memory page allocated to the first virtual machine, and store relocation information for the first set of program modules in a global prelink layout map for use by a second virtual machine. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: January 9, 2018
    Assignee: INTEL CORPORATION
    Inventor: Adriaan Van De Ven
  • Patent number: 9785463
    Abstract: Methods and apparatus for using per task time slice information to improve dynamic performance state selection are described. In one embodiment, a new performance state is selected for a process based on one or more previous execution time slice values of the process. Other embodiments are also described.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Adriaan Van De Ven, A. Leonard Brown, Asit K. Mallick
  • Publication number: 20170109645
    Abstract: Embodiments of techniques and systems for performance of predicted actions are described. In embodiments, a predicted action performance engine (“PAE”) may receive one or probabilities of potential actions that may be performed on a computing device. The PAE may also receive a system context for the computing device describing available resources on the computing device, workload, etc. Based on these probabilities and the system context, the PAE may determine one or more predicted actions and/or resource utilizations which are likely to occur and which may be performed ahead of time. The PAE may then facilitate performance of these actions and/or resource utilizations. Other embodiments may be described and claimed.
    Type: Application
    Filed: October 27, 2016
    Publication date: April 20, 2017
    Inventors: Dirk Hohndel, Adriaan Van De Ven
  • Patent number: 9483308
    Abstract: Embodiments of techniques and systems for performance of predicted actions are described. In embodiments, a predicted action performance engine (“PAE”) may receive one or probabilities of potential actions that may be performed on a computing device. The PAE may also receive a system context for the computing device describing available resources on the computing device, workload, etc. Based on these probabilities and the system context, the PAE may determine one or more predicted actions and/or resource utilizations which are likely to occur and which may be performed ahead of time. The PAE may then facilitate performance of these actions and/or resource utilizations. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: November 1, 2016
    Assignee: Intel Corporation
    Inventors: Dirk Hohndel, Adriaan Van De Ven
  • Publication number: 20160308892
    Abstract: Technologies are provided in embodiments to detect malware. Embodiments are to receive context information related to a potentially affected system, create a prediction of normal traffic based, at least in part, on the received context information, compare network traffic associated with the potentially affected system to the prediction of normal traffic, and take an action based, at least in part, on the comparison. The action may be taken if the network traffic is not within an acceptable deviation range of the prediction of normal traffic or the action may be taken based on a degree of deviation of the network traffic from the prediction of normal traffic. The acceptable deviation range and the degree of deviation are based, at least in part, on a type of network traffic. The acceptable deviation range and the degree of deviation are based, at least in part, on a volume of network traffic.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Applicant: Intel Corporation
    Inventors: Dirk Hohndel, Adriaan van de Ven