Patents by Inventor Adrian Hartog
Adrian Hartog has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7057620Abstract: A method and apparatus for graphics rendered in a mobile device includes a command queue capable of receiving a plurality of rendering commands, a generate_event command and a wait_until command. The wait_until command corresponds to the completion of a specific operation indicated by the generate_event command. The method and apparatus further includes a direct memory access device operably coupled to the command queue, wherein the DMA device is capable of receiving a memory access command in response to the generate_event command. A memory device is capable of storing rendering information, wherein the memory device is accessible in response to the generate_event command. Furthermore, the method and apparatus includes the command queue capable of queuing the rendering commands in response to the wait_until command until the completion of the operation indicated by the generate_event command.Type: GrantFiled: August 25, 2003Date of Patent: June 6, 2006Assignee: ATI Technologies Inc.Inventors: Milivoje Aleksic, Adrian Hartog
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Publication number: 20050046633Abstract: A method and apparatus for graphics rendered in a mobile device includes a command queue capable of receiving a plurality of rendering commands, a generate_event command and a wait_until command. The wait_until command corresponds to the completion of a specific operation indicated by the generate_event command. The method and apparatus further includes a direct memory access device operably coupled to the command queue, wherein the DMA device is capable of receiving a memory access command in response to the generate_event command. A memory device is capable of storing rendering information, wherein the memory device is accessible in response to the generate_event command. Furthermore, the method and apparatus includes the command queue capable of queuing the rendering commands in response to the wait_until command until the completion of the operation indicated by the generate_event command.Type: ApplicationFiled: August 25, 2003Publication date: March 3, 2005Applicant: ATI Technologies, Inc.Inventors: Milivoje Aleksic, Adrian Hartog
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Patent number: 6756988Abstract: A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.Type: GrantFiled: August 6, 1999Date of Patent: June 29, 2004Assignee: ATI International SRLInventors: Chun Wang, Raymond Li, Adrian Hartog, Daniel Gudmundson
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Patent number: 6532525Abstract: A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M commands per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data at a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four-times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.Type: GrantFiled: September 29, 2000Date of Patent: March 11, 2003Assignee: ATI Technologies, Inc.Inventors: Milivoje Aleksic, Grigory Temkine, Oleg Drapkin, Carl Mizuyabu, Adrian Hartog
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Patent number: 6502173Abstract: A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M command per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.Type: GrantFiled: September 29, 2000Date of Patent: December 31, 2002Assignee: ATI Technologies, Inc.Inventors: Milivoje Aleksic, Grigory Temkine, Oleg Drapkin, Carl Mizuyabu, Adrian Hartog
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Patent number: 6445394Abstract: A memory system and method uses common memory for multiple controllers associated with, for example, differing data manipulation functions, such as video graphics related functions or other suitable functions. A multiplexer, configured as a time slicer, selects data for transfer with the memory over a first bus at a first rate. The multichannel serializer is coupled between the multiplexer and a plurality of controllers through a plurality of second buses. Each of the second buses is associated with a different channel. The multichannel serializer has a serializer for each of the plurality of second buses wherein each of the serializers transfers data associated with a channel at a second rate associated with a corresponding controller.Type: GrantFiled: December 15, 1998Date of Patent: September 3, 2002Assignee: ATI International SRLInventors: Hugh Chow, Milivoje M. Aleksic, Adrian Hartog
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Patent number: 6344856Abstract: A method of providing text data for display in a processor controlled apparatus comprised of storing data defining a text character in a memory, in packed monochrome bit map form, addressing the memory to read the text character data, providing the text character to a graphics processor circuit, performing a bitblt operation on each bit of the text character while providing a color attribute, and storing the packed text character having a color attribute for subsequent display.Type: GrantFiled: April 20, 1995Date of Patent: February 5, 2002Assignee: ATI Technologies Inc.Inventors: Sanford S. Lum, Adrian Hartog, Fridtjof Martin Georg Weigel, Josh Grossman, Dan O. Gudmundson
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Patent number: 6184906Abstract: A multiple pipeline memory controller has a plurality of two stage pipeline processors dedicated to separately process real time video capture and display refresh input request signals. A separate pipeline processor processes non-real time input signals. The multiple pipeline design reduces memory access latency and improves throughput of data in display FIFO memory to effect improved resolution. The multiple pipeline memory controller can be integrated in a video graphics controller (VGC).Type: GrantFiled: June 30, 1997Date of Patent: February 6, 2001Assignee: ATI Technologies, Inc.Inventors: Chun Wang, Raymond Li, Adrian Hartog, Daniel Gudmundson
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Patent number: 5953020Abstract: A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.Type: GrantFiled: June 30, 1997Date of Patent: September 14, 1999Assignee: ATI Technologies, Inc.Inventors: Chun Wang, Raymond Li, Adrian Hartog, Daniel Gudmundson
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Patent number: 5946715Abstract: A method of addressing a computer subsystem memory comprised of establishing an aperture having a predetermined page size, addressing the memory at address boundaries defining multiples of half the page size, and reading or writing a page of data from or to the subsystem memory using the established aperture at consecutive memory locations beginning at one of the boundaries.Type: GrantFiled: September 23, 1994Date of Patent: August 31, 1999Assignee: ATI Technologies Inc.Inventors: Adrian Hartog, Sanford S. Lum, Fridtjof Martin Georg Weigel
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Patent number: 5812143Abstract: A method of performing a bit block transfer (Bitblt) comprised of reading a pixel data sequence from a source trajectory, writing an X coordinate portion of the pixel data sequence to a destination trajectory, repeating the writing step to the end of a scan line in the event the X coordinate portion is smaller than the scan line, reset the X coordinate following the end of the scan line, reset a Y coordinate and write a successive X coordinate portion of the pixel data sequence to the destination register from an X coordinate start position when the Y coordinate actually advances in the pixel data sequence.Type: GrantFiled: July 7, 1997Date of Patent: September 22, 1998Assignee: ATI Technologies Inc.Inventors: Sanford S. Lum, Adrian Hartog, Jerzy Kielbasinski, Fridtjof Martin Georg Weigel