Abstract: Operations within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device.

Abstract: The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon to output data and when the device has stabilized. Waiting for the DLL delay interval to stabilize before locking the delay interval still allows the DLL to immediately and effectively resume operations when the DLL is needed to synchronize the output of the DRAM device with the system clock. The DLL delay interval can be locked, together with the DLL clock, after the DRAM device is deselected by the chip select control line, after a number of no operation commands have been received, and/or after any command issued to the DRAM device has been completed.

Abstract: Some embodiments include apparatus, systems, and methods having a voltage generator to generate a voltage, a memory cell including a storage node associated with a storage node voltage, and a power controller to provide a signal to the voltage generator such that the voltage generated by the voltage generator rises from a voltage less than a reference voltage to a voltage less than the storage node voltage, and such that the voltage generated by the voltage generator is less than or equal to the storage node voltage, at least partially in response to the apparatus entering into a mode. Other embodiments are described.

Abstract: Apparatus, systems, and methods are disclosed, such as those that operate within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device using a different method. Additional apparatus, systems, and methods are disclosed.

Abstract: Data bits stored in memory cells are recognized by an ECC generator as data bit strings in a first direction and data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC controller identifies a data bit string in the first direction having more than one data bit in error based on a respective correction code in the first direction and identifies a data bit string in the second direction having more than one data bit in error based on a respective correction code in the second direction, and causes the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed.

Abstract: Operations within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device.

Abstract: Some embodiments include apparatus, systems, and methods having a voltage generator to generate a voltage, a memory cell including a storage node associated with a storage node voltage, and a power controller to provide a signal to the voltage generator such that the voltage generated by the voltage generator rises from a voltage less than a reference voltage to a voltage less than the storage node voltage, and such that the voltage generated by the voltage generator is less than or equal to the storage node voltage, at least partially in response to the apparatus entering into a mode. Other embodiments are described.

Abstract: Data bits stored in memory cells are recognized by an ECC generator as data bit strings in a first direction and data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC controller identifies a data bit string in the first direction having more than one data bit in error based on a respective correction code in the first direction and identifies a data bit string in the second direction having more than one data bit in error based on a respective correction code in the second direction, and causes the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed.

Abstract: An error correction circuit coupled to a plurality of memory cells in a memory device includes an error correcting code (“ECC”) generator and an ECC controller. The ECC generator is coupled to the memory cells and recognizes data bits stored in the memory cells as a plurality of data bit strings in a first direction and as a plurality of data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC generator generates a respective correction code in the first direction for each data bit string in the first direction and also generates a respective correction code in the second direction for each data bit string in the second direction. The ECC controller is coupled to the memory cells and the ECC generator.

Abstract: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.

Abstract: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.

Abstract: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.

Abstract: The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon to output data and when the device has stabilized. Waiting for the DLL delay interval to stabilize before locking the delay interval still allows the DLL to immediately and effectively resume operations when the DLL is needed to synchronize the output of the DRAM device with the system clock. The DLL delay interval can be locked, together with the DLL clock, after the DRAM device is deselected by the chip select control line, after a number of no operation commands have been received, and/or after any command issued to the DRAM device has been completed.

Abstract: The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon to output data and when the device has stabilized. Waiting for the DLL delay interval to stabilize before locking the delay interval still allows the DLL to immediately and effectively resume operations when the DLL is needed to synchronize the output of the DRAM device with the system clock. The DLL delay interval can be locked, together with the DLL clock, after the DRAM device is deselected by the chip select control line, after a number of no operation commands have been received, and/or after any command issued to the DRAM device has been completed.

Abstract: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.

Abstract: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.

Abstract: Apparatus, systems, and methods are disclosed, such as those that operate within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device using a different method. Additional apparatus, systems, and methods are disclosed.

Abstract: An error correction circuit coupled to a plurality of memory cells in a memory device includes an error correcting code (“ECC”) generator and an ECC controller. The ECC generator is coupled to the memory cells and recognizes data bits stored in the memory cells as a plurality of data bit strings in a first direction and as a plurality of data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC generator generates a respective correction code in the first direction for each data bit string in the first direction and also generates a respective correction code in the second direction for each data bit string in the second direction. The ECC controller is coupled to the memory cells and the ECC generator.

Abstract: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.

Abstract: The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon to output data and when the device has stabilized. Waiting for the DLL delay interval to stabilize before locking the delay interval still allows the DLL to immediately and effectively resume operations when the DLL is needed to synchronize the output of the DRAM device with the system clock. The DLL delay interval can be locked, together with the DLL clock, after the DRAM device is deselected by the chip select control line, after a number of no operation commands have been received, and/or after any command issued to the DRAM device has been completed.