Abstract: Temporal compression of a digital video data stream with hierarchically searching in at least one search unit for pixels in a reference picture to find a best match for the current macroblock. This is followed by constructing a motion vector between the current macroblock and the best match macroblock in the reference picture.

Abstract: A method of and apparatus for identifying a Dual Prime motion estimation best match and generating motion vectors pertaining thereto for inter-picture video compression in a motion picture having images of F.sub.1 and F.sub.2 parities. The Dual Prime method of motion estimation described herein includes a method of generating motion vectors. The motion vectors point from a macroblock in a current field to a macroblock in a past field for inter-picture video compression in a motion picture having images of F.sub.1 and F.sub.2 parities. The first step in the method is defining a macroblock in a parity field of the current picture. Next, the preceding field of the same or opposite parity is searched to find a first best match macroblock in the preceding field. Once a best match macroblock is found, a vector is formed from the current macroblock in the current parity field to the first best match macroblock in the preceding parity field.

Abstract: A detector detects the end of a serial bit stream wherein the serial bit stream is based on one clock and the detector (and other associated circuitry) is based on a different, asynchronous clock. An Exclusive OR block receives the serial bit stream and a digital strobe signal according to IEEE High Performance Serial Bus Specification 1394. Based on this standard, one but not both of the serial bit stream and digital strobe signal changes level every data interval. The Exclusive OR block outputs a periodic signal when the serial bit stream and digital strobe signal are present but outputs a constant digital level upon termination of the serial bit stream and digital strobe signal. The detector also includes a first register coupled to receive the output of the receiver, a second register coupled to receive the output of the first register and a third register coupled to receive the output of the second register. All three registers are clocked simultaneously.

Abstract: A device converts serial data based on one clock to parallel data based on a different, asynchronous clock. The data converter comprises one register bank including first and second registers and another register bank including third and fourth registers. A data input of the first register and a data input of the third register are coupled to receive the serial data. A data input of the second register is coupled to a data output of the first register. A data input of the fourth register is coupled to a data output of the third register. A first clock triggers the first and second registers simultaneously and a second clock triggers the third and fourth registers simultaneously. The first and second clocks alternate with each other. Fifth, sixth, seventh and eighth registers have respective data inputs coupled to respective data outputs of the first, second, third and fourth registers.

Abstract: A scalable architecture MPEG2 compliant digital video encoder system having an I-frame only video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. For IPB bitstreams the system includes a second processor element with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element motion estimation. The system can be in the form of a single integrated circuit chip, or a plurality of integrated circuit chips, that is one for each processor, the I-frame video encoder module, the second processor element, and the third processor element. There can be one or more of the third processor units.