Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

Abstract: An integrated circuit includes a clock management unit that selectively provides a clock signal, an energy management circuit that provides an internal power supply voltage to an internal voltage rail in response to an external power supply voltage, and has a capacitor coupled between the internal voltage rail and a reference voltage terminal, and a clocked digital circuit that is coupled to the internal voltage rail and the reference voltage terminal and operates in synchronism with the clock signal. The clock management unit provides the clock signal at a first frequency during a standby state, continuously at a second frequency higher than the first frequency during an active state, and during a first clock cycle following an end of the standby state while suppressing the clock signal during at least one subsequent clock cycle during a transition state between the standby state and the active state.

Abstract: An integrated circuit is provided with at least one processing unit (TM), a cache memory (L2 BANK) having a plurality of memory modules, and remapping means (RM) for performing an unrestricted remapping within said plurality of memory modules. Accordingly, faulty modules can be remapped without limitations in order to optimise the utilization of the memory modules by providing an even distribution of the faulty modules.

Abstract: An electronic device is provided which comprises a plurality of processing units (IP1-IP6) and a flit-synchronous network-based interconnect (N) for coupling the processing units (IP1-IP6). The network-based interconnect (N) comprises at least one first and at least one second link. The at least one second link comprises N pipeline stages. The communication via the at least one second link and the N pipeline stages constitutes a word-asynchronous communication.

Abstract: An image processing apparatus (400) comprises a SIMD processor (401) which scans an image frame for regions of interest (step 301), for example corresponding to regions having objects or lines of interest. Each region of interest is rescanned to an orthogonal grid. The orthogonal grids are then floorplanned so that they are rearranged into a smaller subset of image lines. The floorplanning consists of mapping a set of rectangles into a compressed frame portion. Optionally, the rectangles can be rotated in order to allow the rectangles to be packed more densely. The SIMD processor (401) then processes the floorplanned image data (step 307). Once the image data has been processed by the SIMD processor, the DSP (405) re-associates the processed data (step 309), using information stored during floorplanning. The image processing apparatus results in a more efficient use of the SIMD processor (401).

Abstract: A data processing circuit contains a register file (17) with a write port and a pipeline of instruction processing stages (10a-d). A timing circuit (14) is arranged to time transfer of instruction dependent information between the stages at mutually different time points, so that processing of successive instructions in respective stages partially overlaps. A first and a second one of the stages (10c,d) are in series in the pipeline. Each of the first and a second one of the stages has a result output for writing a result to the write port, if instruction dependent information in the stage concerned (10c,d) requires writing. A write sequencing circuit (144) performs write tests alternately for instruction dependent information in the first and second one of the stages (10c,d). When the write sequencing circuit (144) performs the write test for a particular one of the stages (10c,d), it tests whether the instruction dependent information in the particular one of the stages (10c,d) requires writing of a result.

Abstract: An electronic circuit is provided that comprises first and second combinational logic blocks and a latch positioned between the combinational logic blocks; wherein the electronic circuit is adapted to operate in a normal mode in which the latch is opened and closed in response to an enable signal, and a test mode in which the latch is held open.

Abstract: The present invention relates to a digital signal processing apparatus comprising a plurality of available hardware resource means and a first instruction set means having access to said available hardware resource means, so that at least a part of said hardware resource means execute operations under control of said first instruction set means, and further comprising a second instruction set means having access to only a predetermined limited subset of said plurality of available hardware resource means, so that at least a part of said predetermined limited subset of said hardware resource means execute operations under control of said second instruction set means.

Abstract: A signal processing device and method of supplying a signal processing result to a plurality of registers arranged in different register files. A plurality of different register files are selected based on a corresponding indication in said instruction word and the register address is supplied to said selected register files. Result values can be broadcasted to multiple registers in a single processor cycle while a copy operation between different register files is eliminated. Broadcasting is thus implemented via overlapping register address spaces, since physical registers having the same logical register address are provided in different register files.

Abstract: The present invention relates to a compiling method and system for generating a sequence of program instructions for use in a processing architecture with architecture resources executing instructions from a corresponding instruction set. A retargetable compiler is used to generate a code using at least two instruction sets in the same processing architecture. One instruction set for a compact code and one for a parallel high performance code. The compact instruction set (Compact Instruction Format) covers a subset (RF11, ALU1, L/S1, BU1) of the architecture, whereas the complete instruction set covers the entire architecture (RF1, UC1, UC2, RF2, UC3, UC4, RF3, UC5, UC6, RF4, UC7). By using the at least two instruction sets of different sizes, the compiler is able to reduce the processed average code length, since fewer bits are needed in the compact code to encode operations and registers.

Abstract: The problem of mis-match between a program counter (14) of a CPU (10) and a byte code counter (18) of an instruction path coprocessor (IPC) (16) is addressed by causing the IPC (16) to translate IPC branch instructions to the CPU branch instructions, in which the CPU branch instructions implicitly indicate whether a corresponding IPC branch instructions should be taken and in which the CPU branch instruction will cause the CPU (10) to set its own program counter (14) to a safe location in the IPC range to avoid overflow.

Abstract: An instruction path coprocessor (IPC) (16) observes the value of a CPU program counter (14) of a CPU (10) to detect whether the IPC (16) should be active. The IPC(1 6) uses the value of the CPU program counter also to determine how the IPC should update its own IPC program counter. When a function is called, an exception or interrupt is handled or a jump to a target specified in a register is executed, an address is prepared that, when loaded into the CPU program counter, will cause the IPC to update its IPC program counter as required for the return from function call, exception or interrupt or jump. The prepared address is loaded into the CPU (10) program counter.

Abstract: The present invention relates to a signal processing device and method of supplying a signal processing result to a plurality of registers arranged in different register files, wherein a plurality of different register files are selected based on a corresponding indication in said instruction word, and the register address is supplied to said selected register files. Thereby, result values can be broadcasted to multiple registers in a single processor cycle, while a copy operation between different register files is eliminated. Broadcasting is thus implemented via overlapping register address spaces, since physical registers having the same logical register address are provided in different register files.

Abstract: The present invention relates to a digital signal processing apparatus comprising a plurality of available hardware resource means and a first instruction set means having access to said available hardware resource means, so that at least a part of said hardware resource means execute operations under control of said first instruction set means, and further comprising a second instruction set means having access to only a predetermined limited subset of said plurality of available hardware resource means, so that at least a part of said predetermined limited subset of said hardware resource means execute operations under control of said second instruction set means.

Abstract: The present invention relates to a compiling method and system for generating a sequence of program instructions for use in a processing architecture with architecture resources executing instructions from a corresponding instruction set. A retargetable compiler is used to generate a code using at least two instruction sets in the same processing architecture. One instruction set for a compact code and one for a parallel high performance code. The compact instruction set (Compact Instruction Format) covers a subset (RF11, ALU1, L/S1, BU1) of the architecture, whereas the complete instruction set covers the entire architecture (RF1, UC1, UC2, RF2, UC3, UC4, RF3, UC5, UC6, RF4, UC7). By using the at least two instruction sets of different sizes, the compiler is able to reduce the processed average code length, since fewer bits are needed in the compact code to encode operations and registers.