Patents by Inventor Adriel Jebin Jacob Jebaraj

Adriel Jebin Jacob Jebaraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11735549
    Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: August 22, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Suresh Yeruva, Owen R. Fay, Sameer S. Vadhavkar, Adriel Jebin Jacob Jebaraj, Wayne H. Huang
  • Patent number: 11587938
    Abstract: Some embodiments include a capacitor having a container-shaped bottom portion. The bottom portion has a first region over a second region. The first region is thinner than the second region. The first region is a leaker region and the second region is a bottom electrode region. The bottom portion has an interior surface that extends along the first and second regions. An insulative material extends into the container shape. The insulative material lines the interior surface of the container shape. A conductive plug extends into the container shape and is adjacent the insulative material. A conductive structure extends across the conductive plug, the insulative material and the first region of the bottom portion. The conductive structure directly contacts the insulative material and the first region of the bottom portion, and is electrically coupled with the conductive plug. Some embodiments include methods of forming assemblies.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael Mutch, Sanket S. Kelkar, Ashonita A. Chavan, Sameer Chhajed, Adriel Jebin Jacob Jebaraj
  • Publication number: 20210391343
    Abstract: Some embodiments include a capacitor having a container-shaped bottom portion. The bottom portion has a first region over a second region. The first region is thinner than the second region. The first region is a leaker region and the second region is a bottom electrode region. The bottom portion has an interior surface that extends along the first and second regions. An insulative material extends into the container shape. The insulative material lines the interior surface of the container shape. A conductive plug extends into the container shape and is adjacent the insulative material. A conductive structure extends across the conductive plug, the insulative material and the first region of the bottom portion. The conductive structure directly contacts the insulative material and the first region of the bottom portion, and is electrically coupled with the conductive plug. Some embodiments include methods of forming assemblies.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 16, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Michael Mutch, Sanket S. Kelkar, Ashonita A. Chavan, Sameer Chhajed, Adriel Jebin Jacob Jebaraj
  • Publication number: 20210343670
    Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.
    Type: Application
    Filed: July 15, 2021
    Publication date: November 4, 2021
    Inventors: Suresh Yeruva, Owen R. Fay, Sameer S. Vadhavkar, Adriel Jebin Jacob Jebaraj, Wayne H. Huang
  • Patent number: 11081460
    Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Suresh Yeruva, Owen R. Fay, Sameer S. Vadhavkar, Adriel Jebin Jacob Jebaraj, Wayne H. Huang
  • Patent number: 10978306
    Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Adriel Jebin Jacob Jebaraj, Brian J. Kerley, Sanjeev Sapra, Ashwin Panday
  • Publication number: 20200312954
    Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Jerome A. Imonigie, Adriel Jebin Jacob Jebaraj, Brian J. Kerley, Sanjeev Sapra, Ashwin Panday
  • Publication number: 20200211993
    Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Suresh Yeruva, Owen R. Fay, Sameer S. Vadhavkar, Adriel Jebin Jacob Jebaraj, Wayne H. Huang