Patents by Inventor Ae-nee JANG
Ae-nee JANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200126930Abstract: A semiconductor device in which reliability and production yield are improved by reducing or preventing the spreading of cracks that may occur in the die sawing process, and a method for fabricating the same are provided. The semiconductor device includes a substrate which includes a first chip region and a scribe lane region surrounding the first chip region, a first low-k insulating film, which includes a first insulating material having a dielectric constant lower than silicon oxide, on the substrate in the first chip region, a wiring structure, which includes a second low-k insulating film including the first insulating material and a first wiring pattern in the second low-k insulating film, on the substrate in the scribe lane region, and a first protective insulating film, which includes a second insulating material different from the first insulating material, between the first low-k insulating film and the wiring structure.Type: ApplicationFiled: July 16, 2019Publication date: April 23, 2020Inventors: Yun Rae Cho, Ae Nee Jang, Seung Hun Han
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Publication number: 20200051932Abstract: A semiconductor device has a semiconductor chip region which contains a semiconductor chip and a first portion of a passivation film covering the semiconductor chip and a scribe line region which contains a second portion of the passivation film connected to the first portion of the passivation film, a first insulating film protruding from a distal end of the second portion of the passivation film, and at least a part of a first wiring. A first portion of the first insulating film is disposed along the distal end of the second portion of the passivation film, a second portion of the first insulating film protrudes laterally beyond the first portion of the first insulating film, and the first wiring protrudes laterally beyond the second portion of the first insulating film.Type: ApplicationFiled: August 6, 2019Publication date: February 13, 2020Inventors: SEUNG HUN HAN, YUN RAE CHO, NAM GYU BAEK, AE NEE JANG
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Publication number: 20200035649Abstract: A semiconductor package includes a package substrate, a plurality of external connections under the package substrate, a master chip on the package substrate, at least one slave chip on the master chip, a plurality of first bumps and a plurality of second bumps between the package substrate and the master chip, and a plurality of wires connecting the package substrate to the at least one slave chip. The package substrate includes a plurality of first paths connecting the plurality of first bumps to the plurality of external connections and a plurality of second paths connecting the plurality of second bumps to the plurality of wires. An upper surface of the package substrate includes a first edge and a second edge that extend in a first direction and a third edge and a fourth edge that extend in a second direction.Type: ApplicationFiled: April 5, 2019Publication date: January 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ae-nee JANG, Nam-gyu BAEK, Yun-rae CHO, Seung-hun HAN
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Publication number: 20190164922Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.Type: ApplicationFiled: January 10, 2019Publication date: May 30, 2019Inventors: Ae-nee JANG, KyungSeon HWANG, SunWon KANG
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Patent number: 10211176Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.Type: GrantFiled: December 12, 2016Date of Patent: February 19, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ae-nee Jang, KyungSeon Hwang, SunWon Kang
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Patent number: 9859204Abstract: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.Type: GrantFiled: August 8, 2016Date of Patent: January 2, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong Soon Park, Hyunsoo Chung, Won-young Kim, Ae-nee Jang, Chanho Lee
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Publication number: 20170179062Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.Type: ApplicationFiled: December 12, 2016Publication date: June 22, 2017Inventors: Ae-nee JANG, KyungSeon HWANG, SunWon KANG
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Publication number: 20170084559Abstract: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.Type: ApplicationFiled: August 8, 2016Publication date: March 23, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Myeong Soon Park, Hyunsoo Chung, Won-young Kim, Ae-nee Jang, Chanho Lee
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Patent number: 9570423Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.Type: GrantFiled: December 2, 2015Date of Patent: February 14, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-yong Jang, Young-lyong Kim, Ae-nee Jang
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Patent number: 9373574Abstract: Disclosed are semiconductor packages and methods of forming the same. In the semiconductor packages and the methods, a package substrate includes a hole not overlapped with semiconductor chips. Thus, a molding layer may be formed without a void.Type: GrantFiled: July 3, 2013Date of Patent: June 21, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ae-nee Jang, Young Lyong Kim, Jaegwon Jang
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Patent number: 9343437Abstract: Semiconductor package devices and methods of forming the semiconductor package devices are provided. The semiconductor package devices may include a lower package including a lower semiconductor chip on a lower substrate, an upper package including an upper semiconductor chip on an upper substrate. The upper substrate may include a protruding part corresponding to the lower semiconductor chip and a connection part that has a bottom surface lower than a bottom surface of the protruding part and is disposed around the protruding part. The semiconductor package devices may also include a heat dissipation part in a space between the lower semiconductor chip and the protruding part on the upper substrate and a package connection pattern electrically connecting the lower package to the upper package.Type: GrantFiled: April 7, 2015Date of Patent: May 17, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Ae-nee Jang, Jin-Woo Park, Seokhyun Lee, Jongho Lee
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Patent number: 9299631Abstract: According to example embodiments, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower semiconductor chip on a top surface of a lower package substrate, lower lands on the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant. Upper solder balls are connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.Type: GrantFiled: May 23, 2014Date of Patent: March 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Ae-Nee Jang, Young-Lyong Kim
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Publication number: 20160086931Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.Type: ApplicationFiled: December 2, 2015Publication date: March 24, 2016Inventors: Chul-yong JANG, Young-lyong KIM, Ae-nee JANG
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Publication number: 20160086924Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.Type: ApplicationFiled: December 2, 2015Publication date: March 24, 2016Inventors: Chul-yong JANG, Young-lyong KIM, Ae-nee JANG
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Publication number: 20160064365Abstract: A semiconductor package includes a package substrate having a lower substrate and an upper substrate disposed on the lower substrate, the package substrate having a first cavity, a first semiconductor chip disposed in the first cavity, and a chip stack disposed to partially cover the first cavity on the upper substrate.Type: ApplicationFiled: February 19, 2015Publication date: March 3, 2016Inventors: JAE-GWON JANG, Seok-Hyun Lee, Ae-Nee Jang
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Patent number: 9245816Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.Type: GrantFiled: July 10, 2014Date of Patent: January 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-yong Jang, Young-lyong Kim, Ae-nee Jang
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Publication number: 20150357298Abstract: A semiconductor chip includes a semiconductor chip die having a first surface and a second surface facing the first surface, a connection pad on the first surface of the semiconductor chip die, and a redistribution pad arranged on the first surface of the semiconductor chip die and electrically connected to the connection pad and including an end portion having a concave-convex structure and extended to a lateral surface of the semiconductor chip die.Type: ApplicationFiled: March 4, 2015Publication date: December 10, 2015Inventors: Jae-Gwon JANG, Jong-Ho LEE, Ae-Nee JANG
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Publication number: 20150318266Abstract: Semiconductor package devices and methods of forming the semiconductor package devices are provided. The semiconductor package devices may include a lower package including a lower semiconductor chip on a lower substrate, an upper package including an upper semiconductor chip on an upper substrate. The upper substrate may include a protruding part corresponding to the lower semiconductor chip and a connection part that has a bottom surface lower than a bottom surface of the protruding part and is disposed around the protruding part. The semiconductor package devices may also include a heat dissipation part in a space between the lower semiconductor chip and the protruding part on the upper substrate and a package connection pattern electrically connecting the lower package to the upper package.Type: ApplicationFiled: April 7, 2015Publication date: November 5, 2015Inventors: Ae-nee Jang, Jin-Woo Park, Seokhyun Lee, Jongho Lee
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Patent number: 9159705Abstract: A semiconductor package includes a package substrate including a substrate connection pad. At least one semiconductor chip includes at least one redistribution layer. The at least one redistribution layer covers at least a portion of a chip connection pad and extends along an upper surface of the at least one semiconductor chip in a first direction in which the chip connection pad faces toward an edge of the at least one semiconductor chip. At least one interconnection line disposed on a side of the at least one semiconductor chip electrically connects the substrate connection pad to the at least one redistribution layer. The at least one redistribution layer includes a protruding portion protruding from the edge of the at least one semiconductor chip to contact the at least one interconnection line.Type: GrantFiled: June 13, 2014Date of Patent: October 13, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-yong Jang, Ae-nee Jang, Young-lyong Kim
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Patent number: 9024448Abstract: A semiconductor package may include a circuit board chip having a through-hole, a semiconductor device mounted on the circuit board chip, and an encapsulant. The encapsulant encapsulates the semiconductor device, fills the through-hole and has an external pattern that is the complement of a mold within which the encapsulant was formed. The external pattern on one side of the package reflects a mold shape that retards the flow of encapsulant material relative to the flow of encapsulant material on the opposite side of the package.Type: GrantFiled: March 5, 2013Date of Patent: May 5, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Gwon Jang, Young-Lyong Kim, Ae-Nee Jang