Abstract: An improved cell layout for a C3MOS circuit with inductive broadbanding positions the inductor at a distance from the active region to improve isolation and aligns the edges of the resistor, inductor, and transistor regions near the common edge of adjacent cells to decrease the length of the cell-to-cell interconnect lines.

Abstract: Method and circuitry for performing a line loop back test includes a receiver, a deserializer, and a low speed parallel loop back data multiplexer selects either the low speed parallel data from the deserializer when in loop back mode or low speed parallel input data when in normal mode. The deserializer produces a low speed clock output signal that is fed to a low speed loop back reference clock multiplexer and also to a low speed loop back clock multiplexer. Both the loop back reference clock multiplexer and the loop back clock multiplexer select the low speed clock output signal from the deserializer when in line loop back mode. A clock multiplying unit converts the output of the low speed loop back reference clock multiplexer into a high speed clock signal. The serializer generates the high speed serial transmitter data in synchronization with the high speed clock signal received from a clock multiplying unit.

Abstract: An improved cell layout for a C3MOS circuit with inductive broadbanding positions the inductor at a distance from the active region to improve isolation and aligns the edges of the resistor, inductor, and transistor regions near the common edge of adjacent cells to decrease the length of the cell-to-cell interconnect lines.

Abstract: An improved cell layout for a C3MOS circuit with inductive broadbanding positions the inductor at a distance from the active region to improve isolation and aligns the edges of the resistor, inductor, and transistor regions near the common edge of adjacent cells to decrease the length of the cell-to-cell interconnect lines.

Abstract: Method and circuitry for performing a line loop back test includes a receiver, a deserializer, and a low speed parallel loop back data multiplexer selects either the low speed parallel data from the deserializer when in loop back mode or low speed parallel input data when in normal mode. The deserializer produces a low speed clock output signal that is fed to a low speed loop back reference clock multiplexer and also to a low speed loop back clock multiplexer. Both the loop back reference clock multiplexer and the loop back clock multiplexer select the low speed clock output signal from the deserializer when in line loop back mode. A clock multiplying unit converts the output of the low speed loop back reference clock multiplexer into a high speed clock signal. The serializer generates the high speed serial transmitter data in synchronization with the high speed clock signal received from a clock multiplying unit.

Abstract: An integrated circuit servo system demodulator that incorporates a high speed gain stage with DC offset cancellation. The gain stage receives a differential voltage signal representing a servo burst and converts the differential voltage signal to a differential current signal by a transconductance amplifier. The differential current signal is full-wave current rectified and converted to a full-wave rectified voltage signal by a transimpedance amplifier. A DC offset cancellation circuit is coupled between the full-wave current rectifier and transimpedance amplifier and functions to mirror and subtract, from the rectified current signal directed to the transimpedance amplifier, any DC leakage current developed by the rectifier which would generate a DC offset voltage through the transimpedance amplifier.

Abstract: A high-speed SCSI input receiver has separate high and low level input buffers, each operating in response to a control voltage that conditions their respective high and low level switching threshold voltages to remain stable about their design values without regard to temperature and process parameter variations. Each of the input buffers includes an input invertor with n-channel and p-channel current source transistors coupled between the output and the respective supply rails. A master circuit includes circuitry that substantially matches the operative circuitry of the input buffer, except that the input and output of the master circuit's invertor element are coupled together so as to define the elements actual switching threshold voltage. This threshold voltage is compared to a design threshold voltage defined by a resistor divider in a comparator.

Abstract: A high-speed SCSI input receiver has separate high and low level input buffers, each operating in response to a control voltage that conditions their respective high and low level switching threshold voltages to remain stable about their design values without regard to temperature and process parameter variations. Each of the input buffers includes an input invertor with n-channel and p-channel current source transistors coupled between the output and the respective supply rails. A master circuit includes circuitry that substantially matches the operative circuitry of the input buffer, except that the input and output of the master circuit's invertor element are coupled together so as to define the elements actual switching threshold voltage. This threshold voltage is compared to a design threshold voltage defined by a resistor divider in a comparator.

Abstract: A transceiver circuit used in connection with a fiber channel serial interface is designed and constructed with transmitter and receiver phase lock loop sections, each acquiring velocity lock with respect to a 106.25 MHz reference clock signal. The transmitter phase lock loop section is maintained in velocity lock during serialization of a 10-bit encoded transmission character. The receiver phase lock loop section is operative in a phase-only mode during de-serialization and byte synchronization of a 1.0625 GHz serial data stream. VCO control voltages of both the transmitter and receiver phase lock loop sections are monitored and evaluated by a comparison circuit such that if the receiver phase lock loop section looses lock, its VCO control voltage will exceed a pre-determined lock range value, triggering an output of the comparison circuit.

Abstract: A high precision charge pump used in a phase-lock loop incorporating a type-IV phase/frequency detector is designed and constructed to substantially eliminate the effects of ringing and glitch errors on the charge pump output current as averaged over a pump-up and pump-down cycle by the type-IV phase/frequency detector. The high precision charge pump is constructed exclusively of transistors of a single polarity (N-channels) that are so matched as to each have the same current characteristics. The current pulse length, absolute magnitude, and waveform envelopes of the charge pumps source and sink currents are defined by matched transistors. When the type-IV phase/frequency detector is operating in quasi flywheel mode, and no phase comparisons are being made, the charge pump's source current is equal to the sink current in all significant respects such that no incremental, residual charge is left on a loop capacitor following the conclusion of a sequential pump-up and pump-down sequence.

Abstract: A phase lock loop includes precision charge pump current generation circuit which provides a dynamically variable charge pump current to a charge pump. The charge pump current is developed from the VCO control voltage and varies in inverse proportionality to changes in the control voltage. The proportionality between the precision current and the control voltage is defined by a bias network and such that the current is inversely proportional to the VCO gain and the phase lock loop bandwidth is therefore maintained at a substantially constant value.