Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, and controllers. Each processor may include a plurality of processor ports and a sync adapter. Each sync adapter may include a plurality of adapter ports. Each controller may include a plurality of controller ports, and a configuration port. The plurality of processors and the plurality of controllers may be coupled together in an interspersed arrangement, and the controllers may be distinct from the processors. Each processor may be configured to send a synchronization signal through its adapter ports to one or more controllers, and to pause execution of program instructions while waiting for a response from the one or more controllers.

Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, and controllers. Each processor may include a plurality of processor ports and a sync adapter. Each sync adapter may include a plurality of adapter ports. Each controller may include a plurality of controller ports, and a configuration port. The plurality of processors and the plurality of controllers may be coupled together in an interspersed arrangement, and the controllers may be distinct from the processors. Each processor may be configured to send a synchronization signal through its adapter ports to one or more controllers, and to pause execution of program instructions while waiting for a response from the one or more controllers.

Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, and controllers. Each processor may include a plurality of processor ports and a sync adapter. Each sync adapter may include a plurality of adapter ports. Each controller may include a plurality of controller ports, and a configuration port. The plurality of processors and the plurality of controllers may be coupled together in an interspersed arrangement, and the controllers may be distinct from the processors. Each processor may be configured to send a synchronization signal through its adapter ports to one or more controllers, and to pause execution of program instructions while waiting for a response from the one or more controllers.

Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, and controllers. Each processor may include a plurality of processor ports and a sync adapter. Each sync adapter may include a plurality of adapter ports. Each controller may include a plurality of controller ports, and a configuration port. The plurality of processors and the plurality of controllers may be coupled together in an interspersed arrangement, and the controllers may be distinct from the processors. Each processor may be configured to send a synchronization signal through its adapter ports to one or more controllers, and to pause execution of program instructions while waiting for a response from the one or more controllers.

Abstract: A method and apparatus for determining access protection (96) includes receiving a plurality of access requests (84) corresponding to a plurality of masters (12, 14), determining access permissions (86), providing state information (60), determining access permissions (86) based on the access request (84), and selectively modifying the access permissions based on the state information (90). The state information (60) may relate to debug operation, operation from unsecure or unverified memories, memory programming, direct memory access operation, boot operation, software security verification, security levels, security monitor operation, operating mode, fault monitor, external bus interface, etc (88).

Abstract: In one embodiment, a data processing system (10) includes a first master, storage circuitry (35) coupled to the first master (12) for use by the first master (12), a first control storage circuit (38) which stores a first prefetch limit (60), a prefetch buffer (42), and prefetch circuitry (40) coupled to the first control storage circuit, to the prefetch buffer, and to the storage circuitry. In one embodiment, the prefetch circuitry (40) selectively prefetches a predetermined number of lines from the storage circuitry into the prefetch buffer (42) based on whether or not a prefetch counter, initially set to a value indicated by the first prefetch limit, has expired. In one embodiment, the first prefetch limit may therefore be used to control how many prefetches occur between misses in the prefetch buffer.

Abstract: A memory controller and method thereof configures a prefetch buffer dynamically for interfacing between multiple bus masters of different burst support and multiple memories having different characteristics. A line size of at least a portion of the prefetch buffer is modified based upon the memory controller receiving a read request from one of the bus masters. An adaptive method to optimally replace prefetch buffer lines uses prioritized status field information to determine which buffer line to replace.

Abstract: A memory controller and method thereof configures a prefetch buffer dynamically for interfacing between multiple bus masters of different burst support and multiple memories having different characteristics. A line size of at least a portion of the prefetch buffer is modified based upon the memory controller receiving a read request from one of the bus masters. An adaptive method to optimally replace prefetch buffer lines uses prioritized status field information to determine which buffer line to replace.

Abstract: The present invention relates generally to data processors and more specifically, to data processors having an adaptive priority controller. One embodiment relates to a method for prioritizing requests in a data processor (12) having a bus interface unit (32). The method includes receiving a first request from a first bus requesting resource (e.g. 30) and a second request from a second bus requesting resource (e.g. 28), and using a threshold corresponding to the first or second bus requesting resource to prioritize the first and second requests. The first and second bus requesting resources may be a push buffer (28) for a cache, a write buffer (30), or an instruction prefetch buffer (24). According to one embodiment, the bus interface unit (32) includes a priority controller (34) that receives the first and second requests, assigns the priority, and stores the threshold in a threshold register (66).

Abstract: A method and apparatus for determining access protection (96) includes receiving a plurality of access requests (84) corresponding to a plurality of masters (12, 14), determining access permissions (86), providing state information (60), determining access permissions (86) based on the access request (84), and selectively modifying the access permissions based on the state information (90). The state information (60) may relate to debug operation, operation from unsecure or unverified memories, memory programming, direct memory access operation, boot operation, software security verification, security levels, security monitor operation, operating mode, fault monitor, external bus interface, etc (88).

Abstract: The present invention relates generally to data processors and more specifically, to data processors having an adaptive priority controller. One embodiment relates to a method for prioritizing requests in a data processor (12) having a bus interface unit (32). The method includes receiving a first request from a first bus requesting resource (e.g. 30) and a second request from a second bus requesting resource (e.g. 28), and using a threshold corresponding to the first or second bus requesting resource to prioritize the first and second requests. The first and second bus requesting resources may be a push buffer (28) for a cache, a write buffer (30), or an instruction prefetch buffer (24). According to one embodiment, the bus interface unit (32) includes a priority controller (34) that receives the first and second requests, assigns the priority, and stores the threshold in a threshold register (66).