Abstract: A shunt regulator for an RFID tag chip is powered from split outputs from the RF rectifier, including a first output for providing a power delivery path to on-chip circuits and a second output for providing a discharge-regulation path. The shunt regulator includes a capacitor coupled between the first output and ground. The shunt regulator further includes an input node for receiving a power supply voltage from the rectifier split outputs, a first diode having an anode coupled to the input node, a second diode having an anode coupled to the input node, a resistor divider circuit and amplifier coupled between a cathode of the first diode and ground, transistor having a control terminal coupled to an output of the resistor divider and amplifier circuit, and a current path coupled between a cathode of the second diode and ground.

Abstract: A bandgap ready circuit for an RFID tag includes a bandgap circuit for providing a bandgap voltage, a first comparator for monitoring first and second voltages in the bandgap circuit and for providing a first logic signal, a second comparator for monitoring third and fourth voltages in the bandgap circuit and for providing a second logic signal, and a logic circuit for combining the first and second logic signals to provide a bandgap ready logic signal.

Abstract: A dynamic adjusting RFID demodulator circuit includes an envelope detector having an input for receiving a modulated RF signal, a fixed reference generator coupled to the input of an RC filter, an RF level dependent signal path adding to the fixed reference level at higher RF energy levels, a comparator having a first input coupled to an output of the envelope detector, a second input coupled to an output of the RC filter, and an output for providing a data output signal.

Abstract: A voltage regulator for low power operation of digital circuits includes an output node for providing a regulated output voltage, a diode-connected P-channel transistor in series with a second diode-connected N-channel transistor coupled between the output node and ground, and a bias current having a value for biasing the first and second diode-connected transistors in a sub-threshold mode of operation. The low power voltage regulator further includes a buffer amplifier or emitter or source follower stage to provide a low impedance regulated voltage. The bias current may be generated by a bandgap circuit.

Abstract: A delay circuit for an RFID tag includes a power supply input and a power supply output and one or more delay circuits in cascade connection between the power supply input and the power supply output. A first delay circuit includes a passive circuit, a second delay circuit includes a ramp circuit, and a third delay circuit includes a current mirror circuit.

Abstract: A clamp circuit for an RFID tag includes a power supply node, a dynamic clamp coupled between the power supply node and ground, and an active clamp coupled between the power supply and ground, having a shunt combined effect for providing a clamped power supply node VDDR voltage. The dynamic clamp includes a capacitor divider circuit, a resistor coupled to the capacitor divider circuit, and an N-channel transistor coupled to the capacitor divider circuit. The active clamp includes a differential amplifier having a first input coupled to a resistor divider, a second input for receiving a reference voltage, and an output coupled to a P-channel transistor for the clamped VDDR voltage.

Abstract: Sequencing circuitry for a ferroelectric RFID circuit includes an input node for receiving an external voltage, a bandgap circuit coupled to the input node, a bandgap ready circuit coupled to the bandgap circuit, a slew filter having an input coupled to the input node and to the bandgap ready circuit, a filter capacitor coupled to an output of the slew filter, and an LDO regulator having an input coupled to the output of the slew filter having a plurality of regulated voltages for use in a memory portion, a digital circuit portion, and for generating a reset signal. The sequencing circuitry further includes delay circuits for introducing a controlled delay between operational modes, POR cells for monitoring power supply voltages, and a digital state machine for monitoring internal nodes to control a shut-down pulse generator.

Abstract: A delay circuit for an RFID tag includes a power supply input and a power supply output and one or more delay circuits in cascade connection between the power supply input and the power supply output. A first delay circuit includes a passive circuit, a second delay circuit includes a ramp circuit, and a third delay circuit includes a current mirror circuit.

Abstract: Sequencing circuitry for a ferroelectric RFID circuit includes an input node for receiving an external voltage, a bandgap circuit coupled to the input node, a bandgap ready circuit coupled to the bandgap circuit, a slew filter having an input coupled to the input node and to the bandgap ready circuit, a filter capacitor coupled to an output of the slew filter, and an LDO regulator having an input coupled to the output of the slew filter having a plurality of regulated voltages for use in a memory portion, a digital circuit portion, and for generating a reset signal. The sequencing circuitry further includes delay circuits for introducing a controlled delay between operational modes, POR cells for monitoring power supply voltages, and a digital state machine for monitoring internal nodes to control a shut-down pulse generator.

Abstract: A voltage regulator for low power operation of digital circuits includes an output node for providing a regulated output voltage, a diode-connected P-channel transistor in series with a second diode-connected N-channel transistor coupled between the output node and ground, and a bias current having a value for biasing the first and second diode-connected transistors in a sub-threshold mode of operation. The low power voltage regulator further includes a buffer amplifier or emitter or source follower stage to provide a low impedance regulated voltage. The bias current may be generated by a bandgap circuit.

Abstract: A dynamic adjusting RFID demodulator circuit includes an envelope detector having an input for receiving a modulated RF signal, a fixed reference generator coupled to the input of an RC filter, an RF level dependent signal path adding to the fixed reference level at higher RF energy levels, a comparator having a first input coupled to an output of the envelope detector, a second input coupled to an output of the RC filter, and an output for providing a data output signal.

Abstract: A bandgap ready circuit for an RFID tag includes a bandgap circuit for providing a bandgap voltage, a first comparator for monitoring first and second voltages in the bandgap circuit and for providing a first logic signal, a second comparator for monitoring third and fourth voltages in the bandgap circuit and for providing a second logic signal, and a logic circuit for combining the first and second logic signals to provide a bandgap ready logic signal.

Abstract: A shunt regulator for an RFID tag chip is powered from split outputs from the RF rectifier, including a first output for providing a power delivery path to on-chip circuits and a second output for providing a discharge-regulation path. The shunt regulator includes a capacitor coupled between the first output and ground. The shunt regulator further includes an input node for receiving a power supply voltage from the rectifier split outputs, a first diode having an anode coupled to the input node, a second diode having an anode coupled to the input node, a resistor divider circuit and amplifier coupled between a cathode of the first diode and ground, transistor having a control terminal coupled to an output of the resistor divider and amplifier circuit, and a current path coupled between a cathode of the second diode and ground.

Abstract: A clamp circuit for an RFID tag includes a power supply node, a dynamic clamp coupled between the power supply node and ground, and an active clamp coupled between the power supply and ground, having a shunt combined effect for providing a clamped power supply node VDDR voltage. The dynamic clamp includes a capacitor divider circuit, a resistor coupled to the capacitor divider circuit, and an N-channel transistor coupled to the capacitor divider circuit. The active clamp includes a differential amplifier having a first input coupled to a resistor divider, a second input for receiving a reference voltage, and an output coupled to a P-channel transistor for the clamped VDDR voltage.

Abstract: A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit.

Abstract: A monocycle forming network may include a monocycle generator, up and down pulse generators, data modulators and clock generation circuits. The network may generate monocycle pulses having very narrow pulse widths, approximately 80 picoseconds peak to peak. The monocycles may be modulated to carry data in ultra-wideband communication systems.

Abstract: A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit.

Abstract: A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit.

Abstract: A mono-cycle generating circuit comprises a control circuit, a multiplexer, and a driver switch circuit. The control circuit generates sets of timing pulses. The multiplexer selects one of the sets of timing pulses. The driver switch circuit outputs a mono-cycle based upon the selected set of timing pulses. The driver switch circuit comprises complementary sets of switches, each complementary set of switches including complementary amplitude pull-up/pull-down functions such that the output mono-cycle is a full rail swing mono-cycle.

Abstract: A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit.