Patents by Inventor Ahmad Hamzehdoost
Ahmad Hamzehdoost has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6468834Abstract: A die-up configuration includes a rigid circuit board with electrically conductive plated-through holes formed therethrough and an integrated-circuit die mounted to the upper surface of which a flexible insulated tape layer is fixed to the upper surface of a rigid circuit board and which has a number of wire-bonding sites. Conductive vias or plated-through holes are provided for connecting the wire-bonding sites on the upper surface of the flexible insulated tape layer to the contact areas formed on the lower surface of the flexible insulated tape layer. Conductors are provided for connecting respective contact areas on the lower surface of the flexible insulated tape layer to solder balls on the bottom of the rigid circuit board.Type: GrantFiled: December 2, 1999Date of Patent: October 22, 2002Inventor: Ahmad Hamzehdoost
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Patent number: 6264778Abstract: One or more reinforcement pins are inserted between the lid and base of a sealed integrated-circuit package. The reinforcement pins reinforce a sealing layer between the lid and the base, particularly against shear forces exerted on the sealing layer between the lid and the base of a package. Shorter pins are provided which do not extend through the lid or base. Longer pins are provided which extend through the lid or base, with the ends of the pins being mechanically secured to the lid or base and sealed with solder, glass, or epoxy material.Type: GrantFiled: July 29, 1994Date of Patent: July 24, 2001Assignee: Philips Electronics North America CorporationInventors: Ahmad Hamzehdoost, Leonard Lucio Mora
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Patent number: 6069407Abstract: A die-up configuration includes a rigid circuit board with electrically conductive plated-through holes formed therethrough and an integrated-circuit die mounted to the upper surface of which a flexible insulated tape layer is fixed to the upper surface of a rigid circuit board and which has a number of wire-bonding sites. Conductive vias or plated-through holes are provided for connecting the wire-bonding sites on the upper surface of the flexible insulated tape layer to the contact areas formed on the lower surface of the flexible insulated tape layer. Conductors are provided for connecting respective contact areas on the lower surface of the flexible insulated tape layer to solder balls on the bottom of the rigid circuit board.Type: GrantFiled: November 18, 1998Date of Patent: May 30, 2000Assignee: VLSI Technology, Inc.Inventor: Ahmad Hamzehdoost
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Patent number: 5999415Abstract: A die-down HBGA package includes an integrated-circuit die mounted to a substantially flat lower surface of a die-carrier/heat spreader. A flexible insulated tape layer with a central opening for the die has its upper surface adhesively fixed to the lower side of the die-carrier/heat spreader. Wire-bonding sites and a number of contact areas are connected by traces on the lower surface of the tape layer. Bonding-wire loops are connected between the wire-bonding pads on the die and the wire-bonding sites on the insulated tape layer. A rigid board, such as an epoxy or ceramic circuit board, with electrically conductive plated-through holes is fixed to the insulated flexible tape layer with adhesive. Conductive adhesive material connects the contact areas with the top surfaces of the plated-through holes. Alternatively, pins join the carrier/heat spreader and the rigid circuit board. Solder pads for solder balls are formed on the bottom surface of the printed-circuit board.Type: GrantFiled: November 18, 1998Date of Patent: December 7, 1999Assignee: VLSI Technology, Inc.Inventor: Ahmad Hamzehdoost
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Patent number: 5910686Abstract: An integrated-circuit die is attached to the top interior surface of a die-cavity formed in the underside of a heat spreader. The other side of the integrated circuit die has a number of wire-bonding pads formed thereupon. A plurality of bonding-wire loops at least some of which are completely contained within the die-cavity to allow the part of the encapsulation or lid to be as thin as possible, while still covering the bonding wires. A first portion of a insulated tape layer covers the lower outside surface of the die-carrier/heat spreader and another portion of the insulated tape layer extends inside of the die-cavity and has a number of wire-bonding sites formed thereupon. A plurality of bonding-wire loops are bonded to one of the wire-bonding pads formed on the integrated-circuit die and the wire-bonding sites formed on the insulated tape layer.Type: GrantFiled: July 23, 1998Date of Patent: June 8, 1999Assignee: VLSI Technology, Inc.Inventors: Ahmad Hamzehdoost, Robert J. Martin
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Patent number: 5742009Abstract: A printed circuit board layout is provided for minimizing signal delays caused by mismatch in length of the inner leads of a package lead frame. This is accomplished by the provision of a unique conductive trace pattern formed preferably on the top surface or else on a lower surface of an electrically-insulated, heat-conducting printed circuit board. The conductive trace pattern includes a plurality of U-shaped metallized traces. Each of the plurality of U-shaped traces have a varying length so that certain ones adjacent the inner leads at the center of the package lead frame are longer than certain ones adjacent the inner leads at the corners of the package lead frame. The conductive trace pattern and the outer leads of the package lead frame also serve to transfer heat away from a molded-plastic body encapsulating an integrated-circuit die and the package lead frame and distribute the same on the printed circuit board.Type: GrantFiled: October 12, 1995Date of Patent: April 21, 1998Assignee: VLSI Technology CorporationInventors: Ahmad Hamzehdoost, Chin-Ching Huang
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Patent number: 5687474Abstract: A package for an integrated-circuit includes a package body having a die-cavity formed therein. A die-attach pad is formed in the package body adjacent the die-cavity. An opening is formed in the central portion of the die-attach pad for exposing one side of the integrated-circuit die so that an external cooling media can directly contact the exposed side of the integrated-circuit die. The die-attach pad can be formed as a die-mounting ring adjacent the die-attach cavity. The peripheral edge of the integrated-circuit die is fixed to a mounting surface on the die-mounting ring portion to accommodate direct cooling of the exposed side of the integrated-circuit die. The mounting surface of the die-mounting ring extends beyond the peripheral edge of the integrated-circuit die to accommodate a range of sizes of the integrated-circuit die.Type: GrantFiled: January 11, 1996Date of Patent: November 18, 1997Assignee: VLSI Technology, Inc.Inventors: Ahmad Hamzehdoost, Leonard Lucio Mora
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Patent number: 5689091Abstract: A multi-layer substrate structure and a method for fabricating the same are provided. Thin metal foils are laminated on the top and bottom sides of a non-conductive layer so as to form a laminated substrate. A plurality of plated-through holes are formed in the laminated substrate and are then filled with an epoxy. The laminated substrate is then patterned and etched. Epoxy layers are disposed on both sides of the laminated substrate. The laminated substrate is formed with a plurality of smaller plated-through holes extending through the epoxy layers and with a cavity to receive an integrated-circuit die. The through holes and the epoxy layers are metallized on both sides of the laminated substrate. The laminated substrate is patterned and etched again. A solder mask is applied on both sides of the laminated substrate so as to form selective wire bondable areas and selective solderable areas. The integrated circuit die is disposed in the center of the cavity and has a plurality of bonding pads.Type: GrantFiled: September 19, 1996Date of Patent: November 18, 1997Assignee: VLSI Technology, Inc.Inventors: Ahmad Hamzehdoost, Kamran Manteghi
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Patent number: 5539151Abstract: One or more reinforcement pins are inserted between the lid and base of a sealed integrated-circuit package. The reinforcement pins reinforce a sealing layer between the lid and the base, particularly against shear forces exerted on the sealing layer between the lid and the base of a package. Shorter pins are provided which do not extend through the lid or base. Longer pins are provided which extend through the lid or base, with the ends of the pins being mechanically secured to the lid or base and sealed with solder, glass, or epoxy material.Type: GrantFiled: July 23, 1993Date of Patent: July 23, 1996Assignee: VLSI Technology, Inc.Inventors: Ahmad Hamzehdoost, Leonard L. Mora
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Patent number: 5491362Abstract: A package for an integrated-circuit includes a package body having a die-cavity formed therein. A die-attach pad is formed in the package body adjacent the die-cavity. An opening is formed in the central portion of the die-attach pad for exposing one side of the integrated-circuit die so that an external cooling media can directly contact the exposed side of the integrated-circuit die. The die-attach pad can be formed as a die-mounting ring adjacent the die-attach cavity. The peripheral edge of the integrated-circuit die is fixed to a mounting surface on the die-mounting ring portion to accommodate direct cooling of the exposed side of the integrated-circuit die. The mounting surface of the die-mounting ring extends beyond the peripheral edge of the integrated-circuit die to accommodate a range of sizes of the integrated-circuit die.Type: GrantFiled: August 13, 1993Date of Patent: February 13, 1996Assignee: VLSI Technology, Inc.Inventors: Ahmad Hamzehdoost, Leonard L. Mora
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Patent number: 5430331Abstract: An integrated-circuit die attached to a thermally conductive substrate having surface variations formed into the surface of the thermally conductive substrate. A lead frame has inwardly-extending fingers, which are attached to the thermally conductive substrate. The integrated circuit die, lead frame, and substrate are enclosed within a mold cavity. The surface variations of the thermally conductive substrate provide for a more balanced flow of plastic material over the top and bottom of the substrate provide a molded package body substantially free of voids.Type: GrantFiled: June 23, 1993Date of Patent: July 4, 1995Assignee: VLSI Technology, Inc.Inventors: Ahmad Hamzehdoost, Sang S. Lee
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Patent number: 5371321Abstract: A package assembly for an integrated circuit die includes a base having a cavity formed therein for receiving an integrated circuit die. The base has a ground-reference conductor. A number of bonding wires are each connected between respective die-bonding pads on the integrated circuit die and corresponding bonding pads formed on the base. The lid has an electrically conductive layer formed on it to cover the integrated circuit die in the cavity formed in the base. The electrically conductive layer formed on the lid is positioned in close proximity to some of the plurality of bonding wires. The electrically conductive layer formed on the lid is connected to the ground-reference conductor of the base. This arrangement reduces both the self-inductances of the one or more conductors and the mutual inductance between the one or more conductors. With this arrangement the electrically conductive layer formed on the lid is grounded to reduce interference being radiated from the electrically conductive layer.Type: GrantFiled: July 22, 1992Date of Patent: December 6, 1994Assignee: VLSI Technology, Inc.Inventors: Ahmad Hamzehdoost, Chin-Ching Huang