Abstract: In approaches for correction of errors introduced in an interconnect circuit, an ECC proxy circuit is coupled between a first interconnect and the second interconnect, and generates for each of the write transactions from a bus master circuit, a first ECC from and associated with data of the write transaction, and transmits the write transaction and associated first ECC on the second interconnect. The ECC proxy circuit also supplements each of the read transactions from the bus master circuit with a reference to a second ECC associated with data referenced by the read transaction. The ECC proxy circuit transmits the read transaction that references the second ECC on the second interconnect. At least one random access memory (RAM) is coupled to the ECC proxy circuit through the second interconnect. The RAM stores data of each write transaction and the first ECC.

Abstract: A method for operating a programmable IC is disclosed. A set of circuits specified by a set of configuration data is operated in a set of programmable resources. In response to one of a set of status signals indicating an error, a value indicative of an error is stored in a respective one of a plurality of error status registers. The values stored in the plurality of error status registers are provided to an error handling circuit included in the set of circuits specified by the set of configuration data and operated in the programmable resources. At least one error handling process is performed by the error handling circuit as a function of values stored in the plurality of error status registers.

Abstract: A very low power real-time clock is provided. The real-time clock includes a real-time clock core and a real-time clock controller, both included in an electronic device. The core is powered both when the electronic device is powered on and when it is powered off. When the electronic device is powered off, the core operates on battery power. The controller is powered off when the electronic device is powered off, to save power. The core maintains a tick count and a seconds count. Because the core is powered on even when the electronic device is powered off, the core continues to update the tick count and seconds count even when the electronic device is powered off. The controller provides access, to external components, to the core. By not powering the controller when the electronic device is powered off, non-core functions do not draw power from a battery.

Abstract: In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.

Abstract: Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor.

Abstract: An apparatus is disclosed that includes a processing sub-system having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits. A power management circuit disables power to the processing sub-system, including the interrupt control circuit, in response to the power-down control signal. The power management circuit enables power to the processing sub-system in response to a power-up control signal. The apparatus also includes a proxy interrupt control circuit configured to generate the power-up control signal in response to receiving a peripheral interrupt and power to the processing sub-system being disabled.

Abstract: A crossbar switch device for a processor block ASIC core and a method for a flush-posted-write(s)-before-read mode thereof are described. Operation for the flush-posted-write(s)-before-read mode is set in a first processor block interface coupled to programmable logic fabric. At least one write command is sent from a transaction initiating device instantiated using the programmable logic fabric to the first processor block interface. The at least one write command is posted in the first processor block interface. At least one write command received is stored in a command queue of the crossbar switch device. A read command initiated by a microprocessor is sent to the crossbar switch device. The at least one write command has an address overlap with the read command with respect to a destination target. The read command is temporarily blocked in the crossbar switch device until a command phase of the at least one write command is completed.

Abstract: A system for implementing a non-volatile input/output (I/O) device based memory can include an interface configured to receive a processor request specifying a data unit. The data unit can be specified by a processor address. The system can include an address-data converter coupled to the interface. The address-data converter can be configured to correlate the processor address of the data unit to a data block within the non-volatile I/O device. The system further can include an I/O controller coupled to the address-data converter. The I/O controller can be configured to issue a non-volatile I/O device command specifying the data block to the non-volatile I/O device.

Abstract: A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar interconnect. The crossbar interconnect provides pipelines for coupling the hardwired core to the programmable circuitry. The microprocessor, the crossbar interconnect, and the memory controller interface are all capable of operating at a first frequency of operation, and the memory controller interface is further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation. The crossbar interconnect is configured to direct transactions initiated by the microprocessor to the memory controller interface for accessing one or more memory devices coupled to the memory controller interface via a memory controller.

Abstract: A method for address acknowledgement is described. A memory controller interface is embedded as part of an embedded core in a host integrated circuit. Access to the memory controller interface is arbitrated with an arbiter. An accept signal is sent from the memory controller interface to the arbiter to indicate whether the memory controller interface is ready to receive a transaction. Access to the memory controller interface is requested by a master device for passing the transaction to a memory controller via the arbiter. The arbiter is a proxy for the memory controller interface responsive to the accept signal being asserted. An acknowledgement signal is sent from the arbiter as a proxy for the memory controller interface responsive to receipt of the transaction and the accept signal being asserted.

Abstract: A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract: An embodiment of a method of enhancing security of internal memory is disclosed. For this embodiment of the method, the application specific block is operated in a functional mode, and a reset of the application specific block is initiated. From a built-in self-test engine, at least one write to the internal memory is initiated in response to the reset initiated, where the at least one write overwrites data stored in the internal memory during a reset mode.

Abstract: A method for decoding, including: obtaining an op-code from a master device; setting a mode to mask a first portion of the bits of the op-code, where the first portion of the bits are for being treated as a wildcard value; and decoding a second portion of the op-code that is not masked to determine whether the op-code is for a slave device. The decoding of the second portion is performed by a controller having a decoder, and the controller bridges the master device for communication with the slave device. The decoding of the first portion of the bits is performed by the slave device. The first portion of the bits identifies an instruction from a group of instructions, and the group of instructions uses a single configuration register of registers of the controller.

Abstract: A method and controller for supporting out of order execution of instructions is described. A microprocessor is coupled to a coprocessor via a controller. Instructions are received by the microprocessor and the controller. Indices respectively associated with the instructions are generated by the microprocessor, and the instructions are popped from the first queue for execution by the coprocessor. The controller includes a first queue and a second queue. The instructions and the indices are queued in the first queue, and this first queuing includes steering the instructions and the indices associated therewith to respective first register locations while maintaining association between the instructions and the indices. The instructions may be popped off the first queue out of order with respect to an order in which the instructions are received into the first queue.

Abstract: A device control register controller for a processor block Application Specific Integrated Circuit (“ASIC”) core is described. Device control register slave blocks are coupled to the device control register controller and have access to device registers for a plurality of interfaces of the processor block ASIC core. A master device interface is for coupling at least one slave device external to the processor block ASIC core to the device control register controller. A slave device interface is for coupling a master device external to the processor block ASIC core to the device control register controller.

Abstract: Command translation of burst commands is described. A slave processor local bus (“PLB”) bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB bridge, has any of a plurality of command bus widths. A burst command is issued via a command bus, having a command bus width of the plurality, from the master device for the slave PLB bridge. The burst command is converted to a native bus width of the slave processor logic block if the command bus width is not equal to the native bus width. The burst command is translated if execution of the burst command will exceed the data size threshold and passed without the translating if the execution of the burst command will not exceed the data size threshold.

Abstract: An ASIC block embedded in a host IC has a first clock domain with a first frequency of operation that is at least equal to a second frequency of operation of a second clock domain in the host IC but external to the ASIC block. FPGA logic in the second clock domain interfaces with the ASIC block; and a PLL located in the host integrated circuit but external to the ASIC block is coupled to receive a reference clock signal and configured to generate clock signals. Two of the clock signals are respectively sent to the FPGA logic and the ASIC block to make one appear to be produced earlier in time than the other with respect to the ASIC block to compensate for a clock insertion delay and for a clock-to-output time associated with the FPGA logic that at least approximates zero.

Abstract: Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.

Abstract: A method of enabling variable latency data transfers in an electronic device, such as an FPGA with an embedded processor, is described. According to one aspect of the invention, a method comprises steps of providing an address for a data transfer between a memory controller and a peripheral device; coupling an address valid signal to the peripheral device; transferring the data between the memory controller and the peripheral device; and receiving a data transfer complete signal at the memory controller. According to another aspect of the invention, an integrated circuit enabling a variable latency data transfer is described. The integrated circuit comprises peripheral device; a memory controller coupled to the peripheral device; an address valid signal coupled from the memory controller to the peripheral device; and a transfer complete signal coupled from the peripheral device to the memory controller.