Patents by Inventor Ahmad R. Ashrafzadeh
Ahmad R. Ashrafzadeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9735768Abstract: In a general aspect, an apparatus can include a temperature measurement circuit configured to produce a first signal indicating a first operating temperature of a first semiconductor device and a temperature comparison circuit operationally coupled with the temperature measurement circuit. The temperature comparison circuit can be configured to compare the first signal with a second signal indicating a second operating temperature of at least a second semiconductor device and produce a comparison signal indicating whether the indicated first operating temperature is higher, lower or equal to the indicated second operating temperature. The apparatus can also include an adjustment circuit configured to adjust operation of the first semiconductor device based on the comparison signal.Type: GrantFiled: July 22, 2014Date of Patent: August 15, 2017Assignee: Fairchild Semiconductor CorporationInventor: Ahmad R. Ashrafzadeh
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Patent number: 9536800Abstract: In one general aspect, a package can include a semiconductor die having a first terminal on a first side of the semiconductor die and a second terminal on a second side of the semiconductor die, a leadframe portion electrically coupled to the second terminal of the semiconductor die, and a molding compound. The first terminal on the first side of the semiconductor die, a first surface of the leadframe portion, and a first surface of the molding compound can define at least a portion of a first surface of the package. A second surface of the molding compound and a second surface of the leadframe portion can define at least a portion of a second surface of the package parallel to the first surface of the package, and the second surface can be on an opposite side of the package from the first surface of the package.Type: GrantFiled: December 4, 2014Date of Patent: January 3, 2017Assignee: Fairchild Semiconductor CorporationInventors: Ahmad R. Ashrafzadeh, Adrian Mikolajczak, Chung-Lin Wu, Maria Cristina Estacio
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Patent number: 9478519Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.Type: GrantFiled: October 30, 2015Date of Patent: October 25, 2016Assignee: Fairchild Semiconductor CorporationInventors: Ahmad R. Ashrafzadeh, Vijay G. Ullal, Justin Chiang, Daniel Kinzer, Michael M. Dube, Oseob Jeon, Chung-Lin Wu, Maria Cristina Estacio
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Patent number: 9367502Abstract: Communication methods and apparatus and power supply controllers using the same. The method includes transferring information over a line from a first location to a second location as a voltage signal while simultaneously transferring information over the same line from the second location to the first location as a current signal. Further, digital information may be transmitted over the same line. When applied to a power supply controller system, a master controller may control a plurality of slave controllers by initially setting up the slave controllers by transmitting digital information to the slave controllers, and then maintaining a set point for each controller while monitoring controller characteristics over the same lines.Type: GrantFiled: May 25, 2012Date of Patent: June 14, 2016Assignee: Maxim Integrated Products, Inc.Inventor: Ahmad R. Ashrafzadeh
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Publication number: 20160126219Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.Type: ApplicationFiled: October 30, 2015Publication date: May 5, 2016Inventors: Ahmad R. ASHRAFZADEH, Vijay G. ULLAL, Justin CHIANG, Daniel KINZER, Michael M. DUBE, Oseob JEON, Chung-Lin WU, Maria Cristina ESTACIO
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Patent number: 9177925Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.Type: GrantFiled: November 27, 2013Date of Patent: November 3, 2015Assignee: Fairfchild Semiconductor CorporationInventors: Ahmad R. Ashrafzadeh, Vijay G. Ullal, Justin Chiang, Daniel Kinzer, Michael M. Dube, Oseob Jeon, Chung-Lin Wu, Maria Cristina Estacio
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Publication number: 20150162270Abstract: In one general aspect, a package can include a semiconductor die having a first terminal on a first side of the semiconductor die and a second terminal on a second side of the semiconductor die, a leadframe portion electrically coupled to the second terminal of the semiconductor die, and a molding compound. The first terminal on the first side of the semiconductor die, a first surface of the leadframe portion, and a first surface of the molding compound can define at least a portion of a first surface of the package. A second surface of the molding compound and a second surface of the leadframe portion can define at least a portion of a second surface of the package parallel to the first surface of the package, and the second surface can be on an opposite side of the package from the first surface of the package.Type: ApplicationFiled: December 4, 2014Publication date: June 11, 2015Inventors: Ahmad R. ASHRAFZADEH, Adrian MIKOLAJCZAK, Chung-Lin WU, Maria Cristina ESTACIO
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Publication number: 20150035384Abstract: In a general aspect, an apparatus can include a temperature measurement circuit configured to produce a first signal indicating a first operating temperature of a first semiconductor device and a temperature comparison circuit operationally coupled with the temperature measurement circuit. The temperature comparison circuit can be configured to compare the first signal with a second signal indicating a second operating temperature of at least a second semiconductor device and produce a comparison signal indicating whether the indicated first operating temperature is higher, lower or equal to the indicated second operating temperature. The apparatus can also include an adjustment circuit configured to adjust operation of the first semiconductor device based on the comparison signal.Type: ApplicationFiled: July 22, 2014Publication date: February 5, 2015Inventor: Ahmad R. ASHRAFZADEH
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Patent number: 8785248Abstract: Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.Type: GrantFiled: January 9, 2012Date of Patent: July 22, 2014Assignee: Maxim Integrated Products, Inc.Inventor: Ahmad R. Ashrafzadeh
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Patent number: 8785244Abstract: Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.Type: GrantFiled: November 29, 2012Date of Patent: July 22, 2014Assignee: Maxim Integrated Products, Inc.Inventor: Ahmad R. Ashrafzadeh
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Publication number: 20130089953Abstract: Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.Type: ApplicationFiled: January 9, 2012Publication date: April 11, 2013Applicant: MAXIM INTEGRATED PRODUCTS, INC.Inventor: Ahmad R. Ashrafzadeh
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Publication number: 20130089951Abstract: Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.Type: ApplicationFiled: November 29, 2012Publication date: April 11, 2013Inventor: Ahmad R. Ashrafzadeh
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Publication number: 20100072615Abstract: The present invention has various aspects relating to the maximization of current carrying capacity of wafer level packaged chip scale solder pad mounted integrated circuits. In one aspect, the solder pad areas are maximized by using rectangular solder pads spaced as close together as reliable mounting to a circuit board will allow. In another aspect, multiple contact pads may be used for increasing the current capacity without using contact pads of different areas. In still another aspect, vias are used to directly connect one lead of high current component or components to a contact pad directly above that component, and to route a second lead of the high current component to an adjacent contact pad by way of a thick metal interconnect layer.Type: ApplicationFiled: September 24, 2008Publication date: March 25, 2010Applicant: MAXIM INTEGRATED PRODUCTS, INC.Inventors: Arkadii V. Samoilov, Duane Thomas Wilcoxen, Viren V. Khandekar, Vivek Jain, Ahmad R. Ashrafzadeh, Mansour Izadinia
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Patent number: 6369559Abstract: A DC converter to connect a first DC voltage to a second DC voltage includes a first switch connected to input the first DC voltage, a second switch connected to the first switch, the first switch and the second switch generating a first main voltage, a third switch connected to the first switch, a fourth switch connected to the third switch, and a latch circuit to control the third switch and to control the fourth switch.Type: GrantFiled: November 15, 2000Date of Patent: April 9, 2002Assignee: Texas Instruments IncorporatedInventor: Ahmad R. Ashrafzadeh