Abstract: A new architecture to fabricate high-rise fully monolithic three-dimensional Integrated-Circuits (3D-ICs) is described. It has the major advantage over all known prior arts in that it substantially reduces RC-delays and fully eliminates or very substantially reduces the large and bulky electrically conductive Through-Silicon-VIAS in a monolithic 3D integration. This enables the 3D-ICs to have faster operational speed with denser device integration.

Abstract: Method to fabricate high-rise three-dimensional Integrated-Circuits (3D-ICs) is described. It has the major advantage over all the other known methods and prior arts to fabricate or manufacture 3D-ICs in that it substantially reduces RC-delays and fully eliminates or very substantially reduces the large and bulky electrically conductive Through-Silicon-VIAs in monolithic 3D integration. This enables the 3D-ICs to have faster operational speed with denser device integration.

Abstract: New Nitride semiconductor epitaxy incorporating high Aluminum content is presented. It incorporated traces of Indium that adequately tuned its lattice size closer to that of a narrower bandgap semiconductor that interfaced it and formed a 2DEG device channel QW. The incorporation of adequate low molar fraction of Indium into AlN compound that possesses strong Spontaneous-Polarization enabled the lattice size of this epitaxy to better match that of the semiconductor interfacing it and did consequently grow thicker and induced very high carrier-concentrations into the device 2DEG QW resulting therefore in highest current densities.

Abstract: New, distinct, and useful architectures for single-legged SOI-MOS were established and fabricated for the very first time. They incorporated into their architectures an innovative new configuration to wire the device Body to the Body-Tied-Source. This new configuration drastically increased the conductance between the Body and the Body-Tied-Source. This consequently allowed these devices to effectively support much higher operating biases. Same configuration also functioned on structures with very large peripheries. These gave proportional increase in this same conductivity, and for same area-efficiency, with the increase of their peripheries to accommodate higher currents. The functional model that governs this proportional scaling in these new architectures for single-legged SOI-MOS devices was established and is being claimed through this patent for the very first time.

Abstract: The invention provides the guided design approach to optimize the device performance for a best area-efficient layout footprint in a single-leg MOS device that is based on any of the SOI, SOS or SON technologies. The design methodology depends on a new proprietary device architecture that is also being claimed in this patent and that allows the implementations of the design equations of our methodology.