Abstract: An analog to digital converter temperature compensation system comprising a comparator configured to compare an analog input signal to a compensated feedback signal and generate a comparator output. A SAR module processes the comparator output to generate a digital signal. A digital to analog converter, biased by a biasing signal having temperature change induced error, is configured to convert the digital signal to a feedback signal and a detector is configured to detect a signal that is proportional to temperature. A look-up table is configured to receive and convert the signal that is proportional to temperature to a compensation signal such that the compensation signal compensates for the temperature change induced error in the biasing signal. A summing node combines the feedback signal with the compensation signal to create a compensated feedback signal.

Abstract: One example discloses a current monitoring device, including: a sense impedance configured to receive a current to be monitored; an impedance divider, coupled to the sense impedance, and configured to convert the current to be monitored to a differential voltage to be monitored; a reference circuit configured to generate a differential reference voltage; a comparator coupled to the impedance divider and the reference circuit and configured to output a signal if the differential voltage to be monitored is different than the differential reference voltage; and wherein the reference circuit includes a comparator trimming circuit configured to vary the differential reference voltage to compensate for offset biases in the comparator.

Abstract: A wide band communications circuit buffer can include a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module, and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the emitter followers before an output of the wide band driver to keep an output level at the output of the wide band buffer close to a desired level. Resistors connected between emitters and a VEE terminal can be used to further adjust the DC level. An LC tank filter can be provided between emitters of the voltage buffer components and the circuit's outputs to pass and boost high frequency signals provided to next stage components. The wide band buffer is, inter alia, appropriate for use in providing a DC level shift function as used in wired data communication systems circuitry.

Abstract: Various embodiments relate to a method for calibration of a center frequency of a BPF in an FSK transceiver, the method including the steps of filtering a carrier frequency signal by the BPF to produce a filtered signal, detecting, by a phase-frequency detector (“PFD”), a difference in phase between the carrier frequency signal and the filtered signal from the BPF, sweeping a calibration code of the BPF, detecting a transition in the sign of the phase difference and capturing a calibration code associated with the transition in the sign of the phase difference for calibration of the BPF.

Abstract: Various embodiments relate to a PLL based FSK demodulator, the FSK demodulator comprising a PFD configured to receive an input signal, a fully differential auxiliary charge pump configured to receive and amplify the input signal from the PFD, a capacitor configured to filter the input signal from the auxiliary charge pump and a fully differential slicer configured to demodulate the input signal and output recovered data.

Abstract: One example discloses a current monitoring device, including: a sense impedance configured to receive a current to be monitored; an impedance divider, coupled to the sense impedance, and configured to convert the current to be monitored to a differential voltage to be monitored; a reference circuit configured to generate a differential reference voltage; a comparator coupled to the impedance divider and the reference circuit and configured to output a signal if the differential voltage to be monitored is different than the differential reference voltage; and wherein the reference circuit includes a comparator trimming circuit configured to vary the differential reference voltage to compensate for offset biases in the comparator.

Abstract: One example discloses an interface circuit, including: an inductive coil having a first, second and third terminal; wherein the first terminal is coupled to an external interface port; wherein the second terminal is coupled to a first communication port; wherein the third terminal is coupled to a second communication port; and wherein the inductive coil is configured to attenuate an equivalent capacitance from at least one of the terminals.

Abstract: A wide band communications circuit buffer can include a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module, and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the emitter followers before an output of the wide band driver to keep an output level at the output of the wide band buffer close to a desired level. Resistors connected between emitters and a VEE terminal can be used to further adjust the DC level. An LC tank filter can be provided between emitters of the voltage buffer components and the circuit's outputs to pass and boost high frequency signals provided to next stage components. The wide band buffer is, inter alia, appropriate for use in providing a DC level shift function as used in wired data communication systems circuitry.

Abstract: Various embodiments relate to a PLL based FSK demodulator, the FSK demodulator comprising a PFD configured to receive an input signal, a fully differential auxiliary charge pump configured to receive and amplify the input signal from the PFD, a capacitor configured to filter the input signal from the auxiliary charge pump and a fully differential slicer configured to demodulate the input signal and output recovered data.

Abstract: Various embodiments relate to a method for calibration of a center frequency of a BPF in an FSK transceiver, the method including the steps of filtering a carrier frequency signal by the BPF to produce a filtered signal, detecting, by a phase-frequency detector (“PFD”), a difference in phase between the carrier frequency signal and the filtered signal from the BPF, sweeping a calibration code of the BPF, detecting a transition in the sign of the phase difference and capturing a calibration code associated with the transition in the sign of the phase difference for calibration of the BPF.

Abstract: A duty cycle correction circuit is disclosed. The duty cycle correction circuit includes an input stage, an output stage and a feedback component including a feedback amplifier and a low pass filter. The feedback component compares and adjusts the duty cycle of a signal from an input stage to a target value via a control voltage. The input stage reduces the rise and fall times of received signal to increase the duty cycle sensitivity to a control voltage from the feedback component. The output of the output stage is coupled to the input of the feedback component and the output stage amplifiers the duty cycle adjusted signal processed by both input stage and feedback component.

Abstract: Embodiments of linear equalizers are disclosed. In an embodiment, a linear equalizer includes sets of transistors, a resistor, and first and second impedance elements. The sets of transistors are connected between at least one input terminal of the linear equalizer and at least one output terminal of the linear equalizer. The resistor is connected to a supply voltage, to the at least one output terminal, and to the sets of transistors. The first and second impedance elements are connected between emitter terminals or source terminals of the sets of transistors and at least one fixed voltage. A peaking gain of the linear equalizer is programmable by adjusting a direct current (DC) component of at least one input signal that is received at the at least one input terminal and that is applied to the sets of transistors.

Abstract: An electronic circuit, including an equalizer circuit to input a differential signal, a rectifier circuit to receive the differential signal and output a first current and a second current, a replica circuit to receive a differential threshold signal and output a third current and a fourth current to compensate for PVT variations in the first and second currents, and a comparator circuit configured to compare a differential voltage generated based on the first, second, third, and fourth currents to determine a loss of signal event of the electronic circuit.

Abstract: One example discloses an interface circuit, including: an inductive coil having a first, second and third terminal; wherein the first terminal is coupled to an external interface port; wherein the second terminal is coupled to a first communication port; wherein the third terminal is coupled to a second communication port; and wherein the inductive coil is configured to attenuate an equivalent capacitance from at least one of the terminals.

Abstract: A clamp circuit disposed between a receptacle and a circuit to be protected when a connector connects to the receptacle, the clamp circuit including a voltage detector configured to determine a level of a surge voltage in comparison to a threshold voltage, the voltage detector including a plurality of field effect transistors (FETs) of a first conductivity type connected in series, a first FET of a second conductivity type and a first resistor in parallel with the plurality of FETs, a second FET of the first conductivity type in parallel with the first FET, and a discharge circuit to discharge the surge voltage when the surge voltage approaches the threshold voltage.

Abstract: A system including a device that is configured to communicate current sourcing capabilities to an external power source over a wired connection containing a plurality of wires. The device includes a power supply circuit configured to provide operating power for the device. A first pull-down circuit is configured to provide a pull-down for a particular wire of the wired connection using a first resistive element that is actively trimmed using the operating power. A second pull-down circuit includes at least one transistor that, in the absence of the operating power, is configured to enable a current path, in response to a gate voltage generated from a voltage on the particular wire, between the particular wire and a second resistive element.

Abstract: A squelch detector, including: an input configured to receive an input signal; a peak detector connected to the input configured to detect a maximum value of the input signal wherein the peak detector includes a refresh input configured to receive a refresh signal to refresh the output of the peak detector, a valley detector connected to the input configured to detect a minimum value of the input signal wherein the valley detector includes a refresh input configured to receive the refresh signal to refresh the output of the valley detector, and a comparator including a first signal input connected to an output of the peak detector, a second input connected to an output of the valley detector, and a first reference input, wherein the comparator is configured to compare a difference between an output of the peak detector and an output of the valley detector and a reference value received at the first reference input and configured to produce an output based upon the comparison.

Abstract: An apparatus includes a swing control circuit, a slew control circuit, and a driver circuit. The swing control circuit is configured and arranged to be powered by an input supply voltage, to receive an input data signal and, in response, to generate a first internal signal having a swing level corresponding to the input supply voltage. The slew control circuit, including a switched capacitor circuit, is configured and arranged to receive the first internal signal and, in response, to generate a second internal signal using the switched capacitor circuit that is configured to set a slew rate for the second internal signal. Further, the driver circuit is configured and arranged to receive the second internal signal and, in response, to generate an output signal that is based upon the swing level and the slew rate of the second internal signal.

Abstract: A system including a device that is configured to communicate current sourcing capabilities to an external power source over a wired connection containing a plurality of wires. The device includes a power supply circuit configured to provide operating power for the device. A first pull-down circuit is configured to provide a pull-down for a particular wire of the wired connection using a first resistive element that is actively trimmed using the operating power. A second pull-down circuit includes at least one transistor that, in the absence of the operating power, is configured to enable a current path, in response to a gate voltage generated from a voltage on the particular wire, between the particular wire and a second resistive element.

Abstract: According to one embodiment, a radio frequency (RF) transceiver includes a local oscillator generator (LOGEN) circuit configured to receive an adaptive supply voltage. The LOGEN circuit is coupled to a variable power supply for providing the adaptive supply voltage. A process monitor for the LOGEN circuit is in communication with the variable power supply through a power supply programming module. As a result, the adaptive supply voltage can be adjusted according to data supplied by the process monitor. A method for adaptively powering a LOGEN circuit comprises providing power to an RF device, monitoring a process corner of said LOGEN circuit, determining a supply voltage corresponding to the process corner, and adjusting the supply voltage to adaptively power the LOGEN circuit.