Abstract: Systems and methods for utilizing power overlay (POL) technology and semiconductor press-pack technology to produce semiconductor packages with higher reliability and power density are provided. A POL structure may interconnect semiconductor devices within a semiconductor package, and certain embodiments may be implemented to reduce the probability of damaging the semiconductor devices during the pressing of the conductive plates. In one embodiment, springs and/or spacers may be used to reduce or control the force applied by an emitter plate onto the semiconductor devices in the package. In another embodiment, the emitter plate may be recessed to exert force on the POL structure, rather than directly against the semiconductor devices. Further, in some embodiments, the conductive layer of the POL structure may be grown to function as an emitter plate, and regions of the conductive layer may be made porous to provide compliance.

Abstract: A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.

Abstract: A micro-electromechanical system (MEMS) switch array for power switching includes an input node, an output node, and a plurality of MEMS switches, wherein the input node and the output node are independently in electrical communication with a portion of the plurality of MEMS switches, and wherein a failure of any one of the plurality of MEMS switches does not render ineffective another MEMS switch within the MEMS switch array.

Abstract: A refrigeration system is provided. The refrigeration system includes at least one thermal blocking thermotunneling device. The thermal blocking thermotunneling device comprises a first and a second surface separated by a nanoscale gap of less than about 20 nm, such that tunneling of electrons causes a unidirectional transfer of heat from the first surface to the second surface. Further, the at least one thermal blocking thermotunneling device has a thermal back path of less than about 70 percent.

Abstract: A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.

Abstract: One embodiment of the invention comprises a MEMS structure further comprising: a MEMS device (240) having a first surface with one or more contact structures (244, 245 and 246) thereon connected to functional elements of the MEMS device (240), a dielectric layer (100) overlying the first surface defining openings therein through which the contact structures (244, 245 and 246) are exposed, a patterned metallization layer (254, 255 and 256) comprising conductive material extending from the contact structures (244, 245 and 246) through the openings in the dielectric layer (100) and onto a surface of the dielectric layer and a first heat sink (190) in thermal communication with the metallization layer (254, 255 and 256).

Abstract: A composite structure having a silicon carbide epitaxial layer is provided. The epitaxial layer includes at least four regions arranged vertically and defining respective interfaces, where each of the regions is characterized by a respective impurity concentration, where the impurity concentrations vary across each of the interfaces, and where each of the impurity concentrations exceeds 1×1017 cm?3 for at least one single impurity in all of the regions.

Abstract: A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

Abstract: A micro-electromechanical system (MEMS) switch array for power switching includes an input node, an output node, and a plurality of MEMS switches, wherein the input node and the output node are independently in electrical communication with a portion of the plurality of MEMS switches, and wherein a failure of any one of the plurality of MEMS switches does not render ineffective another MEMS switch within the MEMS switch array.

Abstract: A transistor switch for a system operating at high frequencies is provided. The transistor switch comprises a graded channel region between a source region and a drain region, the graded channel region configured for providing a low resistance to mobile negative charge carriers moving from the source region to the drain region, wherein the graded channel comprises at least two doping levels.

Abstract: A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

Abstract: A composite structure having a silicon carbide epitaxial layer is provided. The epitaxial layer includes at least four regions arranged vertically and defining respective interfaces, where each of the regions is characterized by a respective impurity concentration, where the impurity concentrations vary across each of the interfaces, and where each of the impurity concentrations exceeds 1×107 cm?3 for at least one single impurity in all of the regions.

Abstract: A method of manufacturing a heat transfer device including providing first and second thermally conductive substrates that are substantially atomically flat, providing a patterned electrical barrier on the first or second thermally conductive substrates and disposing a low work function material on the first or second thermally conductive substrates in an area oriented between the patterned electrical barrier in a configuration in which the first and second thermally conductive substrates are positioned opposite from one another. The method also includes bonding the first and second thermally conductive substrates in the configuration and extracting a plurality of units having opposite sections of the first and second thermally conductive substrates, each unit having a portion of the patterned electrical barrier disposed about the low work function material.

Abstract: A transistor switch for a system operating at high frequencies is provided. The transistor switch comprises a graded channel region between a source region and a drain region, the graded channel region configured for providing a low resistance to mobile negative charge carriers moving from the source region to the drain region, wherein the graded channel comprises at least two doping levels.

Abstract: A method and apparatus generates an enhanced trip time curve capable of capturing both the non-sinusoidal energy and series effects. Relevant data including time, current, and energy is plotted on a three-dimensional set of axes. The resultant three-dimensional representation is useful for representing trip times for a protection device accounting for energy effects, and for determining selectivity in a multi-tier electrical distribution system.

Abstract: An apparatus and method for analyzing an apparatus, typically an electrical distribution system is provided. The apparatus and method is particularly useful for analyzing selective electrical distribution systems. The apparatus is generally a software system including a solver system for generating an output from an input presented to the solver system. The input is a mathematical representation of at least a portion of the electrical distribution system. In one embodiment, the input is presented to a model within the solver system. The model represents at least a portion of the electrical distribution system. The software system is capable of interfacing output data from one or more models with additional models for analyzing generally how devices within an electrical distribution system behave under certain conditions.

Abstract: A method and apparatus generates an enhanced trip time curve capable of capturing both the non-sinusoidal energy and series effects. Relevant data including time, current, and energy is plotted on a three-dimensional set of axes. The resultant three-dimensional representation is useful for representing trip times for a protection device accounting for energy effects, and for determining selectivity in a multi-tier electrical distribution system.

Abstract: A method and apparatus generates an enhanced trip time curve capable of capturing both the non-sinusoidal energy and series effects. Relevant data including time, current, and energy is plotted on a three-dimensional set of axes. The resultant three-dimensional representation is useful for representing trip times for a protection device accounting for energy effects, and for determining selectivity in a multi-tier electrical distribution system.

Abstract: A system for modeling a circuit breaker assembly and its components. The system comprises a computer generated and interactive system model, the system model comprising hierarchically arranged sub-models, each sub-model representing a different circuit breaker function, a first pin for passing simulated load current to the system model, and a second pin for passing simulated load current from the system model.

Abstract: An improved system and method for controlling the temperature of a resistance heater in a heating, ventilation and air-conditioning (“HVAC”) system is disclosed. The control circuit and method includes three separate thermostats per heater leg and are designed to trip at three, sequential pre-selected temperatures to address certain issues associated with prior art designs for thermal overload protection. One of the thermostats is of an automatically resettable type wherein the remaining two are of a “one-shot” design and will remain open until there is human intervention.