Abstract: The invention provides an application specific instruction set processor (ASIP) that uses a Very Long Instruction Word (VLIW) for simultaneously executing a plurality of operations. For simultaneously executing the plurality of operations, the ASIP processor comprises a fetching unit to fetch a long instruction word from an instruction memory unit and an instruction decoder unit that interfaces with the fetching unit and a program address counter. The instruction decoder unit decodes the long instruction word fetched from the instruction memory unit and enables a plurality of sub blocks responsible for execution of a plurality of simultaneous independent operations. The instruction decoder unit of the ASIP is capable of decoding a 32-bit instruction word and executing up to six simultaneous independent operations.

Abstract: The invention provide an application specific instruction-set processor (ASIP) that uses a Very Long Instruction Word (VLIW) for executing atomic application specific instructions. The ASIP includes one or more units for executing a first set of atomic application specific instructions for receiving a first set of data across a plurality of input data ports in a first operation specified in an instruction word. Further, the one or more units execute a second set of atomic application specific instructions for outputting a second set of data across a plurality of output data ports in a second operation specified in the instruction word, wherein an input data port of the plurality of input data ports and a corresponding output data port of the plurality of output data ports share a same address location and are specified as operands in the instruction word. Thus, the first operation and the second operation can occur simultaneously.

Abstract: The invention provide an application specific instruction-set processor (ASIP) that uses a Very Long Instruction Word (VLIW) for executing atomic application specific instructions. The ASIP includes one or more units for executing a first set of atomic application specific instructions for receiving a first set of data across a plurality of input data ports in a first operation specified in an instruction word. Further, the one or more units execute a second set of atomic application specific instructions for outputting a second set of data across a plurality of output data ports in a second operation specified in the instruction word, wherein an input data port of the plurality of input data ports and a corresponding output data port of the plurality of output data ports share a same address location and are specified as operands in the instruction word. Thus, the first operation and the second operation can occur simultaneously.

Abstract: The invention provides an application specific instruction set processor (ASIP) that uses a Very Long Instruction Word (VLIW) for simultaneously executing a plurality of operations. For simultaneously executing the plurality of operations, the ASIP processor comprises a fetching unit to fetch a long instruction word from an instruction memory unit and an instruction decoder unit that interfaces with the fetching unit and a program address counter. The instruction decoder unit decodes the long instruction word fetched from the instruction memory unit and enables a plurality of sub blocks responsible for execution of a plurality of simultaneous independent operations. The instruction decoder unit of the ASIP is capable of decoding a 32-bit instruction word and executing up to six simultaneous independent operations.

Abstract: An automatic gain control circuit is disclosed. The automatic gain control circuit receives a radio frequency signal at an input. The input passes the radio frequency signal to a first gain loop having a changeable gain. A low pass filter filters the radio frequency signal. In a second gain loop, the gain of the filtered signal is adjusted. The automatic gain control circuit includes at least one signal detector for detecting a signal level in the first gain loop and a signal level in the second gain loop. The automatic gain control circuit also includes an adjustment module for adjusting the gain of the first and second gain loops based upon the detected signal levels wherein overall gain of the first and the second gain loops is increased no greater than a predetermined value.

Abstract: A method for controlling the power and/or frequency output of a digital data network's transmitters is described. The method controls the transmitter power and/or frequency output by using line loss information as well as the noise margin at both the central office and remote site sides of the transmission link. The transmitters are controlled to minimize the crosstalk between the interconnections on the network. Measurements are taken of the cable losses and signal-to-noise ratios present on the system and the transmitter power and/or frequency are adjusted to minimize unwanted interactions between transceiver pairs on the network.