Patents by Inventor Ahmed Reda Fridi

Ahmed Reda Fridi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10530373
    Abstract: A transceiver includes a frequency modulation continuous wave generator to generate a frequency sequence and a digital phase locked loop to generate a waveform based on the frequency sequence. The digital phase locked loop includes a plurality of control registers. A main controller captures a reference state defined in the plurality of configuration registers prior to the frequency sequence, initiates the frequency sequence, restores the reference state of the configuration registers after completion of the frequency sequence, and repeats the frequency sequence after restoring the reference state.
    Type: Grant
    Filed: June 1, 2019
    Date of Patent: January 7, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ahmed Reda Fridi, Man Tran
  • Patent number: 6545547
    Abstract: A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer (300) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO non-linearity. Temperature tracking and compensation is also provided. A SAR implementation (100) and an interpolation tuning implementation (200) are also described.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: April 8, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Ahmed Reda Fridi, Abdellatif Bellaouar, Sherif Embabi
  • Publication number: 20020036545
    Abstract: A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer (300) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO non-linearity. Temperature tracking and compensation is also provided. A SAR implementation (100) and an interpolation tuning implementation (200) are also described.
    Type: Application
    Filed: August 13, 2001
    Publication date: March 28, 2002
    Inventors: Ahmed Reda Fridi, Abdellatif Bellaouar, Sherif Embabi
  • Patent number: 6308049
    Abstract: The present invention discusses fractional compensation timing circuitry (15) to track a VCO output frequency, fO, and provide highly effective error cancellation in a fractional-N PLL synthesizer. This output frequency tracking is used to suppress spurious sidebands, commonly known as spurs, in both fixed-band and multi-band wireless transceiver applications which use fractional-N PLL synthesizers. Some of the critical parameters which benefit from this type of PLL include switching time, phase noise, and reference feed-through.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: October 23, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Abdellatif Bellaouar, Khaled M. Sharaf, Ahmed Reda Fridi