Abstract: The rollover prevention system includes a motor having a drive shaft, a gear assembly positioned in communicating relation with the motor, an assembly box for housing the gear assembly, and an electronic control system for controlling the rollover prevention system. The gear assembly includes a drive gear positioned in communicating relation with a reduction gear, the reduction gear positioned on the drive shaft of the motor, a drive pin attached to the drive shaft of the motor, the drive pin having a gear, as well as a rotatable wheel positioned in communicating relation with the gear positioned on the drive pin, and an eccentric disc positioned within the rotatable wheel. The rotatable wheel includes an attachment member positioned on the exterior surface of the rotatable wheel, the attachment member being attached to a driver's seat of a vehicle.

Abstract: A wireless sensor includes an antenna, a sensing element, a tuning circuit, a processing module, a reference circuit block, and a transmitter. The tuning circuit adjusts the RF front-end to compensation for a change in a characteristic of the RF front end caused by the sensing element. The reference circuit block generates a signal based on a low voltage low frequency input that corresponds to a second environmental condition. The processing module generates a first digital value based on the adjustment to the RF front-end, where the first digital value is a representation of the first environmental condition, and generate a second digital value based on the signal, where the second digital value is a representation of the second environmental condition. The transmitter generates the outbound RF signal that includes at least one of the first and second digital values.

Abstract: A passive radio frequency identification (RFID) sensor is provided. This passive RFID sensor includes an inductive loop, a processing module, and a wireless communication module. The inductive loop has an inductive loop impedance that may vary with an environment in which the inductive loop is placed. The processing module couples to the inductive loop and has a tuning module that may vary a reactive component impedance coupled to the inductive loop in order to change a system impedance. The system impedance includes both the inductive loop impedance and the reactive component impedance. The tuning module then produces an impedance value representative of the reactive component impedance. A memory module may store the impedance value which may then later be communicated to an RFID reader via the wireless communication module.

Abstract: A passive radio frequency identification (RFID) sensor is provided. This passive RFID sensor includes at least one antenna, at least one processing module, and a wireless communication module. The at least one antenna has an impedance that may vary with an environment in which the sensor is placed. Additionally, the antenna impedance might be permanently changed in response to an environmental variation or an event. The at least one processing module couples to the antenna and has a tuning module that may vary a reactive component impedance coupled to the antenna in order to change a system impedance. The system impedance includes both the antenna impedance and the reactive component impedance. The tuning module then produces an impedance value representative of the reactive component impedance. A memory module may store the impedance value which may then later be communicated to an RFID reader via the wireless communication module.

Abstract: A power harvesting circuit a p-channel circuit, an n-channel circuit, an AC capacitance circuit, and an output capacitance circuit. The p-channel circuit includes a first diode element, a first diode voltage reduction circuit coupled to reduce a diode voltage of the first diode element, and a first start-up current circuit operably coupled to increase start-up current of the first diode element. The n-channel circuit includes a second diode element, a second diode voltage reduction circuit coupled to reduce a diode voltage of the second diode element, and a second start-up current circuit operably coupled to increase start-up current of the second diode element. The AC coupling capacitance circuit is coupled to the p-channel circuit and the n-channel circuit. The output capacitance circuit is coupled to the p-channel circuit and the n-channel circuit.

Abstract: A power harvesting circuit, a rectifier circuit and a capacitor. The rectifier circuit includes a diode circuit, a diode voltage reduction circuit, and a start up current circuit. The diode circuit passes a current when a received RF signal has a first polarity and to substantially blocks the current when the received RF signal has a second polarity. The diode voltage reduction circuit is operably coupled to reduce a voltage drop of the diode circuit. The start up current circuit operably coupled to reduce the start up current of the diode voltage reduction circuit and/or the diode circuit. The capacitor is operably coupled to convert the rectified signal into a DC supply voltage.

Abstract: A passive radio frequency identification (RFID) sensor is provided. This passive RFID sensor includes at least one antenna, at least one processing module, and a wireless communication module. The at least one antenna has an impedance that may vary with an environment in which the sensor is placed. Additionally, the antenna impedance might be permanently changed in response to an environmental variation or an event. The at least one processing module couples to the antenna and has a tuning module that may vary a reactive component impedance coupled to the antenna in order to change a system impedance. The system impedance includes both the antenna impedance and the reactive component impedance. The tuning module then produces an impedance value representative of the reactive component impedance. A memory module may store the impedance value which may then later be communicated to an RFID reader via the wireless communication module.

Abstract: A method and apparatus for combining an alternating current (AC) coupling technique with a low frequency restoration technique to provide AC coupling with low frequency restoration of the attenuated low frequency content. The low frequency restoration circuit operates to extract low frequency information prior to being high-pass filtered by the AC coupling circuit. The low frequency restoration circuit then buffers the low frequency information through a low frequency restoration amplifier, applies a programmable common mode voltage to the buffered, low frequency information, and then restores the buffered, common mode adjusted, low frequency information to the output of the AC coupling circuit.

Abstract: A high-speed, wide bandwidth data detection circuit includes a phase detection module, a data detection module, a loop filter, and a voltage controlled oscillator. The phase detection module is operably coupled to produce a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock. The phase detection module performs the current mode mathematical manipulations and produces the controlled current in the current domain. The data detection module is operably coupled to produce the detected data based on the incoming data stream and the recovered clock. The loop filter is operably coupled to convert the controlled current into a controlled voltage. The voltage controlled oscillator is operably coupled to convert the control voltage into the recovered clock.

Abstract: A data density independent clock and data recovery system includes a lock phase adjust charge pump operably coupled to receive phase information and transition information from a phase detector and to produce a current signal, responsive to the phase information and transition information, to a loop filter that converts the current signal to a control voltage signal operably coupled to a voltage controlled oscillator that produces a clock signal to the phase detector based on the control voltage signal. The lock phase adjust charge pump includes a phase charge pump, a transition charge pump, a programmable DC bias current sink, and two programmable offset bias current sinks. The transition charge pump includes a programmable transition current sink. The control logic operates under external control to adjust the currents conducted by the transition charge pump, the programmable DC bias current sink, and the two programmable offset bias current sinks.

Abstract: A multiplying phase detector includes a 1st multiplier, a 2nd multiplier and a phase error generation module. The 1st multiplier is operably coupled to multiple an incoming data stream, which is a random data pattern, with a 1st clock, which is in-phase with the incoming stream of data and is one-half the rate of the incoming stream of data, to produce a 1st product. In this instance, the 1st product represents missing transitions in the incoming stream of data. The 2nd multiplier is operably coupled to multiply the 1st product with the incoming data stream to produce a modified stream of data. The phase error generation module is operably coupled to generate a phase error based on the modified stream of data and a 2nd clock, where the phase error represents a phase offset between the modified stream of data and the 2nd clock.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: A clock recovery circuit that operates at a clock speed equal to one-half the input data rate is presented. The clock recovery circuit uses dual input latches to sample the incoming serial data on both the rising edge and falling edge of a half-rate clock signal to provide equivalent full data rate clock recovery. The clock recovery circuit functions to maintain the half-rate clock transitions in the center of the incoming serial data bits. The clock recovery circuit includes a phase detector, charge pump, controlled oscillation module and a feedback module. The phase detector produces information on the phase and data transitions in the incoming data signal to the charge pump. Generally, the circuit is delay insensitive and receives phase and transition information staggered relative to each other.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: A high speed phase detector circuit operating at a clock speed equal to one-half an input data rate (i.e. a half-rate clock) provides phase information and transition information from incoming serial data. The high speed phase detector circuit samples the incoming serial data on both the rising edge and falling edge of the half-rate clock to provide equivalent full high speed data rate sampling. The high speed phase detector circuit generates a delay between the phase information and the transition information. The phase information is produced in a first bit period and the transition information is produced in a second bit period relative to the first bit period.

Abstract: A data density independent clock and data recovery system includes a lock phase adjust charge pump operably coupled to receive phase information and transition information from a phase detector and to produce a current signal, responsive to the phase information and transition information, to a loop filter that converts the current signal to a control voltage signal operably coupled to a voltage controlled oscillator that produces a clock signal to the phase detector based on the control voltage signal. The lock phase adjust charge pump includes a phase charge pump, a transition charge pump, a programmable DC bias current sink, and two programmable offset bias current sinks. The transition charge pump includes a programmable transition current sink. The control logic operates under external control to adjust the currents conducted by the transition charge pump, the programmable DC bias current sink, and the two programmable offset bias current sinks.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: A VCO (110) can be configured to convert an analog input signal (105) to a digital output signal (125). In accordance with the inventive arrangements, the VCO can convert the analog input signal to at least one intermediate signal (130) having a frequency dependent on the analog input signal. A frequency detector (115) can be configured to determine a frequency of at least one intermediate signal. Subsequently, a mapping circuit (120) can be configured to map the determined frequency of the at least one intermediate signal to an output value representing the digital output signal (125).