Patents by Inventor Aiguo Bu

Aiguo Bu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Capacity and density enhancement circuit for sub-threshold memory unit array
    Patent number: 8345468
    Abstract: A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: January 1, 2013
    Assignee: Southeast University
    Inventors: Jie Li, Na Bai, Ming Ling, Aiguo Bu, Chao Wang, Chen Hu
  • CAPACITY AND DENSITY ENHANCEMENT CIRCUIT FOR SUB-THRESHOLD MEMORY UNIT ARRAY
    Publication number: 20120069635
    Abstract: A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.
    Type: Application
    Filed: August 18, 2009
    Publication date: March 22, 2012
    Applicant: SOUTHEAST UNIVERSITY
    Inventors: Jie Li, Na Bai, Ming Ling, Aiguo Bu, Chao Wang, Chen Hu