Abstract: Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping.

Abstract: Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping.

Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

Abstract: A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.

Abstract: A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.

Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

Abstract: A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.

Abstract: A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as out

Abstract: A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as out

Abstract: A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.

Abstract: Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined characteristic along the first path. A second path from the launching cell toward the clock source is back-traced to a common one of the marked cells having the predetermined characteristic. Clock uncertainty is calculated based on the portion of the first path from the common marked cell having the predetermined characteristic to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.

Abstract: An adder based circuit embodied in an integrated circuit includes an input module, a carry module and an output module. The carry module has a minimum depth defined by a recursive expansion of at least one function associated with the carry module based on a variable k derived from a Fibonacci series. Invertor, XOR, XNOR (more preferably, OR(NOT(a),b)) and multiplexer elements are selectively coupled to the input and output modules to configure the adder based circuit as a subtractor, adder-subtractor, incrementor, decrementor, incrementer-decrementor or absolute value calculator. A computer process of designing the adder base circuit recursively expands the functions, and optimization of death, fanout and distribution of negations is performed.

Abstract: The present invention is directed to a system and method of finding Boolean symmetries. In aspects of the present invention, a method, system and computer-readable medium constructs a symmetry tree for any Boolean function. A data structure which describes groups of commutative variables of a Boolean function is called a symmetry tree of the Boolean function.

Abstract: Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined character along the first path. A second path from the launching cell toward the clock source is back-traced to a predetermined marked cell. Clock uncertainty is calculated based on the portion of the first path from the predetermined marked cell to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.

Abstract: A process of optimizing setup and hold time violations comprising resynthesis of data and clock logics coupled to pins of the integrated circuit to optimize setup time violations, and resynthesizing data and clock logics coupled to pins of the integrated circuit to optimize hold time violations. Optimization of setup time violations is performed by resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations, then resynthesis of the data logics of each pin having a setup time violation to optimize the setup time violations, and then resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations. The hold time violations are then optimized by resynthesizing the data logics to optimize the hold time violations, and then resynthesizing the clock logics to optimize the hold time violations.

Abstract: The present invention is directed to a system and method of finding Boolean symmetries. In aspects of the present invention, a method, system and computer-readable medium constructs a symmetry tree for any Boolean function. A data structure which describes groups of commutative variables of a Boolean function is called a symmetry tree of the Boolean function.

Abstract: A process of optimizing setup and hold time violations comprising resynthesis of data and clock logics coupled to pins of the integrated circuit to optimize setup time violations, and resynthesizing data and clock logics coupled to pins of the integrated circuit to optimize hold time violations. Optimization of setup time violations is performed by resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations, then resynthesis of the data logics of each pin having a setup time violation to optimize the setup time violations, and then resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations. The hold time violations are then optimized by resynthesizing the data logics to optimize the hold time violations, and then resynthesizing the clock logics to optimize the hold time violations.

Abstract: A method of testing a floor plan for an integrated circuit prior to resynthesis includes attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has an unreachable pin; and if the least-penalty path is constructed, then attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has a bottleneck.