Patents by Inventor Aiko Mizusawa

Aiko Mizusawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9640478
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: May 2, 2017
    Assignee: AOI ELECTRONICS CO., LTD.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20150318244
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Application
    Filed: June 25, 2015
    Publication date: November 5, 2015
    Applicant: TERA PROBE, INC.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 9070638
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: June 30, 2015
    Assignee: TERA PROBE, INC.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20150008579
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 8, 2015
    Applicant: TERA PROBE, INC.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 8871627
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 28, 2014
    Assignee: Tera Probe, Inc.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20140073090
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 13, 2014
    Applicant: TERAMIKROS, INC.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 8587124
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the pump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: November 19, 2013
    Assignee: Teramikros, Inc.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 7816790
    Abstract: A semiconductor device includes a semiconductor substrate and low dielectric film wiring line laminated structure portions which are provided in regions on the semiconductor substrate except a peripheral portion thereof. Each of the laminated structure portions has a laminated structure of low dielectric films and a plurality of wiring lines. An insulating film is provided on an upper side of the laminated structure portion. Connection pad portions for electrodes are arranged on the insulating film to be electrically connected to the connection pad portions of uppermost wiring lines of the laminated structure portion. Bump electrodes for external connection are provided on the connection pad portions for the electrodes. A sealing film is provided on the insulating film and on the peripheral portion of the semiconductor substrate. Side surfaces of the laminated structure portions are covered with the insulating film or the sealing film.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: October 19, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi
  • Publication number: 20090079072
    Abstract: A semiconductor device includes a semiconductor substrate having an integrated circuit. A low dielectric film wiring line laminated structure portion is provided on the semiconductor substrate except a peripheral portion thereof, and is constituted by low dielectric films and wiring lines. The low dielectric film has a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the laminated structure portion. A connection pad portion is arranged on the insulating film and connected to a connection pad portion of an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film is provided on the insulating film which surrounds the pump electrode and on the peripheral portion of the semiconductor substrate. The side surfaces of the laminated structure portion are covered with the insulating film or the sealing film.
    Type: Application
    Filed: December 13, 2007
    Publication date: March 26, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20090079073
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the pump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Application
    Filed: June 4, 2008
    Publication date: March 26, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20070267743
    Abstract: A semiconductor device includes a semiconductor substrate and low dielectric film wiring line laminated structure portions which are provided in regions on the semiconductor substrate except a peripheral portion thereof. Each of the laminated structure portions has a laminated structure of low dielectric films and a plurality of wiring lines. An insulating film is provided on an upper side of the laminated structure portion. Connection pad portions for electrodes are arranged on the insulating film to be electrically connected to the connection pad portions of uppermost wiring lines of the laminated structure portion. Bump electrodes for external connection are provided on the connection pad portions for the electrodes. A sealing film is provided on the insulating film and on the peripheral portion of the semiconductor substrate. Side surfaces of the laminated structure portions are covered with the insulating film or the sealing film.
    Type: Application
    Filed: December 14, 2006
    Publication date: November 22, 2007
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi