Abstract: A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a plurality of system interface blocks comprising first and second interfaces, wherein the first interface comprises a standard interface interfaced to at least one core system and the second interface comprises an interface interfaced to the system bus, a system bus bridge comprising first and second system bus interfaces wherein the first system bus interface comprises an interface interfaced to the system bus and the second system bus interface comprises a standard interface, an on-chip bus bridge comprising first and second on-chip bus interfaces wherein the first on-chip bus interface comprises a standard interface interfaced to the system bus bridge and the second on-chip bus interface comprises an interface interfaced to the on-chip bus.

Abstract: A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a plurality of system interface blocks comprising first and second interfaces, wherein the first interface comprises a standard interface interfaced to at least one core system and the second interface comprises an interface interfaced to the system bus, a system bus bridge comprising first and second system bus interfaces wherein the first system bus interface comprises an interface interfaced to the system bus and the second system bus interface comprises a standard interface, an on-chip bus bridge comprising first and second on-chip bus interfaces wherein the first on-chip bus interface comprises a standard interface interfaced to the system bus bridge and the second on-chip bus interface comprises an interface interfaced to the on-chip bus.

Abstract: A method and apparatus are provided for optimizing performance of a computer system component design by performance analysis of a simulation of the design. The method of the present invention comprises providing the computer system component design to an analyzing apparatus and carrying out a simulation run of the design. During the simulation run, operation data is generated cycle by cycle, and the generated operation data is collected and stored in a log file. The log file is input to a parser and the operation data is sequentially parsed to produce parsed data. Statistical calculations are then performed on the parsed data, and the performance results are output to the designer in graphical form. The performance information can be used to enhance performance of the computer system component prior to its fabrication.