Abstract: A stackable die mounting system with an efficient interconnect is disclosed that can have a base chip carrier to interconnect a base integrated circuit die to a circuit board on a first side and to a second stacked integrated circuit on a second side. The second side can include a first region having a pad out configuration of a first input output (I/O) to transmit data to be stored by the stacked integrated circuit die. The base chip carrier can have a second region with a pad out of a second I/O that is configured to receive data transmitted by the stacked integrated circuit die wherein the pad out of the second port is translated and rotated about an axis from the pad out of the first region such that a busses with different functions can be vertically integrated from the circuit board.

Abstract: A stackable die mounting system with an efficient interconnect is disclosed that can have a base chip carrier to interconnect a base integrated circuit die to a circuit board on a first side and to a second stacked integrated circuit on a second side. The second side can include a first region having a pad out configuration of a first input output (I/O) to transmit data to be stored by the stacked integrated circuit die. The base chip carrier can have a second region with a pad out of a second I/O that is configured to receive data transmitted by the stacked integrated circuit die wherein the pad out of the second port is translated and rotated about an axis from the pad out of the first region such that a busses with different functions can be vertically integrated from the circuit board.