Abstract: A DRAM is provided that can carry out data reads or writes in a constant and short access time regardless of the timing with which the reads or writes, or refreshing are executed. When requests for reads from or writes to burst data are continuously input, row decoding (RD) and column decoding (CD) by a row decoder 42 and a column decoder 52, an array access (AR) and precharging (PR) by a data line driver 24, a bit switch 26, and a sense amplifier 28, and data transfer (TR) by a write buffer 52 and a read buffer 54 are executed in parallel in a pipelined manner. When the time has come to refresh a DRAM array 22, a refresh address held in a refresh controller 40 is output while the burst data is being transferred, and a series of refreshing operations comprising (RD), (AR), and (PR) is performed.