Abstract: Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.

Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

Abstract: Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.

Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

Abstract: Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method of determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function.

Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

Abstract: Disclosed are methods and apparatus for determining whether to perform burn-in on a semiconductor product, such as a product wafer or product wafer lot. In general terms, test structures on the semiconductor product are inspected to extract yield information, such as defect densities. Since this yield information is related to the early or extrinsic instantaneous failure rate, one may then determine the instantaneous extrinsic failure rate for one or more failure mechanisms, such as electromigration, gate oxide breakdown, or hot carrier injection, based on this yield information. It is then determined whether to perform burn-in on the semiconductor product based on the determined instantaneous failure rate.

Abstract: Disclosed is a method for detecting electrical defects on test structures of a semiconductor die. The test structures includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. The test structures each has a portion located partially within a scan area. The portion of the test structures located within the scan area is scanned to obtain voltage contrast images of the test structures' portions. In a multi-pixel processor, the obtained voltage contrast images are analyzed to determine whether there are defects present within the test structures. In a preferred embodiment, the multi-pixel processor operates with pixel resolution sizes in a range of about 25 nm to 200 nm. In another aspect, the processor operates with a pixel size nominally equivalent to two times a width of the test structure's line width to maximize throughput at optimal signal to noise sensitivity.

Abstract: Disclosed are methods and apparatus for efficiently managing IC chip yield learning. In general terms, as each wafer lot moves through fabrication, yield information is obtained from each set of test structures for a particular process or defect mechanism. The nature of the yield information is such that it may be used directly or indirectly to predict product wafer test yield. In one implementation, the yield information includes a systematic yield (Y0), a defect density (DD), and a defect clustering factor (&agr;) determined based on the inspected test structure's yield. A running average of the yield information for each process or defect mechanism is maintained as each wafer lot is processed. As a particular wafer lot moves through the various processes, a product wafer-sort test yield may be predicted at any stage in the fabrication process based on the running-average yield information maintained for previously fabricated wafer lots.

Abstract: Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element. In another embodiment, a semiconductor die having a scanning area is disclosed.

Abstract: Disclosed is a method of inspecting a sample. The method includes moving to a first field associated with a first group of test structures. The first group of test structures are partially within the first field. The method further includes scanning the first field to determine whether there are any defects present within the first group of test structures. When it is determined that there are defects within the first group of test structures, the method further includes repeatedly stepping to areas and scanning such areas so as to determine a specific defect location within the first group of test structures. A suitable test structure for performing this method is also disclosed.

Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

Abstract: Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.

Abstract: Disclosed are methods and apparatus for determining whether to perform burn-in on a semiconductor product, such as a product wafer or product wafer lot. In general terms, test structures on the semiconductor product are inspected to extract yield information, such as defect densities. Since this yield information is related to the early or extrinsic instantaneous failure rate, one may then determine the instantaneous extrinsic failure rate for one or more failure mechanisms, such as electromigration, gate oxide breakdown, or hot carrier injection, based on this yield information. It is then determined whether to perform burn-in on the semiconductor product based on the determined instantaneous failure rate.

Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Abstract: A sample is inspected. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Abstract: An electromagnetic wave-shielding thermoplastic resin composition comprising(A) 100 parts by weight of a thermoplastic resin selected from the group consisting of polypropylene resins, polystyrene resins, acrylonitrile/styrene/butadiene copolymer resin, polybutylene terephthalate resins, polyphenylene ether resins and linear aliphatic polyamide resins,(B) 30 to 300 parts by weight of electrically conductive glass fibers,(C) 5 to 40 parts by weight of carbon black, and(D) 5 to 40 parts by weight of graphite.