Abstract: Systems and methods for reserving bandwidth in a USB hub are disclosed. The systems and methods may include receiving data from at least one downstream endpoint in a buffer, identifying a current capacity of the buffer, comparing the current capacity of the buffer to a buffer threshold, generating an output based at least on the comparison, based at least on the output, dynamically throttling at least one low-throughput endpoint, and allocating a predefined bandwidth to a USB device that has a predetermined bandwidth requirement by providing bandwidth to the USB device available from the throttle of the at least one low-throughput endpoints.

Abstract: An Automatic System Clock Detection System (ASCDS) may provide integrated circuits (ICs) with the capability to detect the frequency of an external crystal oscillator or clock source, and adjust the IC's internal PLL accordingly for proper IC operation. The frequency detection and PLL adjustment may be performed without any additional pins on the IC, and/or without requiring any additional external information. The ASCDS may be configured with an internal ring oscillator, which may be generated from standard logic elements, a watchdog counter, and an input clock counter. When the IC comes out of power on reset (POR), the ASCDS may compare the input clock counter with the watchdog counter, and determine the clock frequency of the input clock. It may then set the PLL parameters to ensure correct IC operation.

Abstract: An Automatic System Clock Detection System (ASCDS) may provide integrated circuits (ICs) with the capability to detect the frequency of an external crystal oscillator or clock source, and adjust the IC's internal PLL accordingly for proper IC operation. The frequency detection and PLL adjustment may be performed without any additional pins on the IC, and/or without requiring any additional external information. The ASCDS may be configured with an internal ring oscillator, which may be generated from standard logic elements, a watchdog counter, and an input clock counter. When the IC comes out of power on reset (POR), the ASCDS may compare the input clock counter with the watchdog counter, and determine the clock frequency of the input clock. It may then set the PLL parameters to ensure correct IC operation.

Abstract: In various embodiments, devices coupled to upstream ports may enumerate the USB switching hub according to the total number of downstream ports on the USB switching hub. In some embodiments, when a first upstream port is communicating with a first downstream port, status registers coupled to the second upstream port may indicate to the second upstream device that the first downstream port is disconnected. By enumerating the USB switching hub according to the total number of downstream ports, the upstream devices may not have to re-enumerate the hub (and correspondingly each device coupled to the hub) each time a downstream device is switched. In some embodiments, an intelligent port routing switch may delay switching communications for the downstream port if there is an active transfer in progress between a related downstream port and an upstream port.