Patents by Inventor Aki Dote
Aki Dote has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111833Abstract: A storing unit stores, amongst coefficients, values of a coefficient group associated with one selected from multiple variable groups, which are obtained by dividing state variables of an evaluation function. A searching unit searches for a solution to an optimization problem by repeating update processing, which includes calculating, using the values of the coefficient group, a value change of the evaluation function responsive to changing the value of each state variable of the variable group and changing the value of one state variable thereof based on the value change and temperature. A processing unit calculates multiplicity indicating the iteration count in which the values of the variable group are maintained in a search using Markov chain Monte Carlo (MCMC), and causes, responsive to cumulated multiplicity exceeding a threshold, the searching unit to perform the update processing using the values of the coefficient group associated with a different variable group.Type: ApplicationFiled: September 25, 2023Publication date: April 4, 2024Applicants: Fujitsu Limited, THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTOInventors: Sigeng CHEN, Jeffrey Seth ROSENTHAL, Ali SHEIKHOLESLAMIi, Hirotaka TAMURA, Aki DOTE
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Publication number: 20230315488Abstract: An optimization device including: a memory; and a processor coupled to the memory, the processor being configured to perform processing, the processing including: holding each of values of a plurality of state variables included in an evaluation function; performing calculation processing including calculating change values of the evaluation function when any one of the values of the plurality of state variables changes with a probability based on a weight value of each of the plurality of state variables, and calculating evaluation values that evaluate which state transition to accept among the plurality of state variables, based on the calculated change values and correction values that correspond to susceptibility to change in the state variables of which the values have been changed; and changing one of the held values of any one of the state variables among the plurality of state variables, based on the calculated evaluation values.Type: ApplicationFiled: December 9, 2022Publication date: October 5, 2023Applicant: Fujitsu LimitedInventor: Aki DOTE
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Publication number: 20220366011Abstract: A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process that includes executing search processing that repeatedly execute selecting, determining, and state changing according to a predetermined order for searching for a solution to a problem represented by an energy function including a plurality of state variables. The search processing includes counting a number of times it is determined that the value of the state variable of a change candidate is not to be continuously changed, and correcting, with an offset, a change amount of the energy function corresponding to the change in the value of the state variable of the change candidate when the counted number of times reaches a predetermined number. The determining includes determine, after the change amount is corrected, whether to change the value of the state variable of the change candidate based on the corrected change amount is performed.Type: ApplicationFiled: February 3, 2022Publication date: November 17, 2022Applicant: FUJITSU LIMITEDInventor: Aki DOTE
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Patent number: 11334646Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: hold values of a plurality of state variables included in an evaluation function representing energy, and outputs, every certain number of trials, the values of the plurality of state variables; compute, when a state transition occurs in response to changing of one of the values of the plurality of state variables, an energy change value for each state transition based on a weight value selected based on an update index value; and determine a first offset value based on a plurality of the energy change values such that at least one of the state transitions is allowed, outputs a plurality of first evaluation values obtained by adding the first offset value to the plurality of energy change values, and outputs, every certain number of trials, the first offset value.Type: GrantFiled: February 20, 2020Date of Patent: May 17, 2022Assignee: FUJITSU LIMITEDInventors: Aki Dote, Hirotaka Tamura
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Publication number: 20210319154Abstract: A sampling method includes: executing a state update process; executing a repetition count calculation process; executing an exchange control process; and executing an output process, the state update process being configured to hold values of a plurality of state variable groups each including a plurality of state variables, the plurality of state variables being included in an evaluation function indicating energy of an Ising model, and generate a state transition by changing any of the plurality of state variables in each attempt on the basis of a temperature value, in which different values are respectively associated with the plurality of state variable groups, and an amount of change in the energy due to a change in any of the plurality of state variables, the output process being configured to output values of the plurality of state variables and an expected value at a predetermined interval.Type: ApplicationFiled: February 2, 2021Publication date: October 14, 2021Applicant: FUJITSU LIMITEDInventors: Aki Dote, Hirotaka Tamura
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Publication number: 20200272682Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: hold values of a plurality of state variables included in an evaluation function representing energy, and outputs, every certain number of trials, the values of the plurality of state variables; compute, when a state transition occurs in response to changing of one of the values of the plurality of state variables, an energy change value for each state transition based on a weight value selected based on an update index value; and determine a first offset value based on a plurality of the energy change values such that at least one of the state transitions is allowed, outputs a plurality of first evaluation values obtained by adding the first offset value to the plurality of energy change values and outputs, every certain number of trials the first offset value.Type: ApplicationFiled: February 20, 2020Publication date: August 27, 2020Applicant: FUJITSU LIMITEDInventors: Aki Dote, Hirotaka TAMURA
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Patent number: 10388632Abstract: A semiconductor device includes, a plurality of semiconductor dies formed using semiconductor substrates, plane orientations of which are the same, and the plurality of the semiconductor dies are stacked such that a crystal orientation of at least one layer is different from other layers.Type: GrantFiled: June 11, 2018Date of Patent: August 20, 2019Assignee: FUJITSU LIMITEDInventor: Aki Dote
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Patent number: 10319667Abstract: An electronic device includes: a substrate that includes a first penetration hole; a first electrode that is located on a first surface of the substrate so as to cover the first penetration hole; and a first penetrating electrode that is located in the first penetration hole and is in contact with or away from the first electrode depending on temperature.Type: GrantFiled: July 5, 2017Date of Patent: June 11, 2019Assignee: FUJITSU LIMITEDInventors: Shoichi Miyahara, Aki Dote, Hideki Kitada
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Patent number: 10283434Abstract: An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.Type: GrantFiled: October 20, 2016Date of Patent: May 7, 2019Assignee: FUJITSU LIMITEDInventors: Taiji Sakai, Seiki Sakuyama, Nobuhiro Imaizumi, Aki Dote
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Publication number: 20180366445Abstract: A semiconductor device includes, a plurality of semiconductor dies formed using semiconductor substrates, plane orientations of which are the same, and the plurality of the semiconductor dies are stacked such that a crystal orientation of at least one layer is different from other layers.Type: ApplicationFiled: June 11, 2018Publication date: December 20, 2018Applicant: FUJITSU LIMITEDInventor: Aki Dote
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Patent number: 10008436Abstract: A semiconductor device includes: a semiconductor substrate; a wiring layer provided on a front-surface side of the semiconductor substrate; a through-via that penetrates through the semiconductor substrate from a back-surface side of the semiconductor substrate and is coupled to a wire included in the wiring layer; and a stress relaxation part that protrudes toward a through-via side and is disposed on a section in the wire and coupled to the through-via, the stress relaxation part including at least one insulating portion containing an insulating material having a smaller thermal expansion coefficient than a material of the through-via.Type: GrantFiled: March 25, 2016Date of Patent: June 26, 2018Assignee: FUJITSU LIMITEDInventors: Aki Dote, Takeshi Ishitsuka, Hideki Kitada
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Publication number: 20180061740Abstract: An electronic device includes: a substrate that includes a first penetration hole; a first electrode that is located on a first surface of the substrate so as to cover the first penetration hole; and a first penetrating electrode that is located in the first penetration hole and is in contact with or away from the first electrode depending on temperature.Type: ApplicationFiled: July 5, 2017Publication date: March 1, 2018Applicant: FUJITSU LIMITEDInventors: Shoichi Miyahara, Aki Dote, Hideki Kitada
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Publication number: 20170125359Abstract: An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.Type: ApplicationFiled: October 20, 2016Publication date: May 4, 2017Applicant: FUJITSU LIMITEDInventors: Taiji Sakai, Seiki Sakuyama, Nobuhiro Imaizumi, Aki Dote
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Patent number: 9596767Abstract: An electronic component includes: a substrate; wiring provided on the substrate, and including an uneven section at an edge portion of the wiring in plain view; and an insulating film provided on the substrate and on the wiring. And a method of manufacturing an electronic component includes: forming, on a substrate, wiring including an uneven section at an edge portion of the wiring in plain view; and forming an insulating film on the substrate and on the wiring.Type: GrantFiled: May 29, 2015Date of Patent: March 14, 2017Assignee: FUJITSU LIMITEDInventor: Aki Dote
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Publication number: 20160351474Abstract: A semiconductor device includes: a semiconductor substrate; a wiring layer provided on a front-surface side of the semiconductor substrate; a through-via that penetrates through the semiconductor substrate from a back-surface side of the semiconductor substrate and is coupled to a wire included in the wiring layer; and a stress relaxation part that protrudes toward a through-via side and is disposed on a section in the wire and coupled to the through-via, the stress relaxation part including at least one insulating portion containing an insulating material having a smaller thermal expansion coefficient than a material of the through-via.Type: ApplicationFiled: March 25, 2016Publication date: December 1, 2016Applicant: FUJITSU LIMITEDInventors: Aki Dote, Takeshi ISHITSUKA, Hideki Kitada
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Publication number: 20150373850Abstract: An electronic component includes: a substrate; wiring provided on the substrate, and including an uneven section at an edge portion of the wiring in plain view; and an insulating film provided on the substrate and on the wiring. And a method of manufacturing an electronic component includes: forming, on a substrate, wiring including an uneven section at an edge portion of the wiring in plain view; and forming an insulating film on the substrate and on the wiring.Type: ApplicationFiled: May 29, 2015Publication date: December 24, 2015Applicant: FUJITSU LIMITEDInventor: Aki Dote
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Patent number: 8652854Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.Type: GrantFiled: March 12, 2012Date of Patent: February 18, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
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Patent number: 8324671Abstract: A semiconductor device has a ferroelectric capacitor having a ferroelectric film, an interlayer insulating film having a first layer formed on the ferroelectric capacitor, a plug and a wiring connecting to the ferroelectric capacitor, and a dummy plug in the vicinity of the ferroelectric capacitor.Type: GrantFiled: February 13, 2008Date of Patent: December 4, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Aki Dote, Kazutoshi Izumi
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Publication number: 20120171785Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.Type: ApplicationFiled: March 12, 2012Publication date: July 5, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
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Patent number: 8153448Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.Type: GrantFiled: May 12, 2009Date of Patent: April 10, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai