Patents by Inventor Akifumi Gawase
Akifumi Gawase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10991588Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes bringing a first catalyst into contact with a workpiece to form an oxide film on a surface of the workpiece, and bringing a second catalyst different from the first catalyst and the oxide film into contact with each other or moving the second catalyst and the oxide film closer to each other to elute the oxide film into a treatment liquid.Type: GrantFiled: November 6, 2017Date of Patent: April 27, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Akifumi Gawase, Yukiteru Matsui, Takahiko Kawasaki
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Patent number: 10985027Abstract: A method for manufacturing a semiconductor device according to an embodiment includes: forming a first layer on a semiconductor substrate, a surface of the first layer having a first plane of which distance from the semiconductor substrate is a first distance and a second plane of which distance from the semiconductor substrate is a second distance smaller than the first distance, and a difference between the first distance and the second distance being 30 nm or more; performing planarization processing on the first layer to have the difference of less than 30 nm; forming a second layer directly on the first layer after performing the planarization processing; supplying a resist to the second layer; bringing a template having a pattern into contact with the resist to form a resist layer to which the pattern has been transferred; and etching the second layer using the resist layer as a mask.Type: GrantFiled: March 17, 2020Date of Patent: April 20, 2021Assignee: Kioxia CorporationInventors: Akifumi Gawase, Yukiteru Matsui, Mikiya Sakashita
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Publication number: 20210087669Abstract: A film forming apparatus according to an embodiment includes: a process chamber forming a film on a substrate; an abatement device detoxifying a first exhaust gas exhausted from the process chamber; a first supply pipe for supplying a gas containing water to the process chamber; a first vacuum pump provided in a first flow path of the first exhaust gas between the process chamber and the abatement device; a second vacuum pump provided in the first flow path between the first vacuum pump and the abatement device; and a first detector provided in the first flow path between the second vacuum pump and the abatement device and capable of detecting a hydrogenated gas.Type: ApplicationFiled: August 26, 2020Publication date: March 25, 2021Applicant: Kioxia CorporationInventors: Yuta KONNO, Toshihiko Nagase, Atsuko Sakata, Kohei Nagata, Ryohei Kitao, Akifumi Gawase, Takeshi Iwasaki
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Publication number: 20210082711Abstract: A method for manufacturing a semiconductor device according to an embodiment includes: forming a first layer on a semiconductor substrate, a surface of the first layer having a first plane of which distance from the semiconductor substrate is a first distance and a second plane of which distance from the semiconductor substrate is a second distance smaller than the first distance, and a difference between the first distance and the second distance being 30 nm or more; performing planarization processing on the first layer to have the difference of less than 30 nm; forming a second layer directly on the first layer after performing the planarization processing; supplying a resist to the second layer; bringing a template having a pattern into contact with the resist to form a resist layer to which the pattern has been transferred; and etching the second layer using the resist layer as a mask.Type: ApplicationFiled: March 17, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Akifumi GAWASE, Yukiteru MATSUI, Mikiya SAKASHITA
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Patent number: 10850363Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes detecting elastic waves, and detecting or predicting an abnormality of the processing object occurring during polishing of the processing object. The elastic waves are generated from the processing object during the polishing. The abnormality is detected or predicted by analyzing the detected elastic waves.Type: GrantFiled: September 2, 2015Date of Patent: December 1, 2020Assignee: Toshiba Memory CorporationInventors: Yukiteru Matsui, Takahiko Kawasaki, Akifumi Gawase, Shuji Suzuki, Tsutomu Miki
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Publication number: 20200298363Abstract: A polishing device includes a substrate holder, a dispenser configured to dispense an abrasive to a surface of a substrate held by the substrate holder, a polisher including an elastic body configured to polish the surface of the substrate as the elastic body is rotated with respect to the surface of the substrate. An area of contact between the elastic body and the surface of the substrate during polishing is smaller than a surface area of a region of the substrate that is to be polished by the elastic body. The elastic body is moved, while the elastic body is rotated, with a downward velocity component prior to contacting the surface of the substrate and with an upward velocity component after the elastic body comes into contact with the surface of the substrate.Type: ApplicationFiled: August 30, 2019Publication date: September 24, 2020Inventor: Akifumi GAWASE
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Publication number: 20200035636Abstract: A semiconductor device production method includes forming a first recess portion in a first insulating film formed on a first substrate and a first conductive layer on the front surface of the first insulating film located inside and outside the first recess portion. In the first recess portion, a first pad is formed having a width of 3 ?m or less and including the first conductive layer by performing a first polishing the first conductive layer at a first polishing rate and, after the first polishing, a second polishing the first conductive layer at a second polishing rate lower than the first polishing rate. The first pad of the first substrate and a second pad of a second substrate are joined together by annealing the first substrate and the second substrate. The selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4.Type: ApplicationFiled: February 28, 2019Publication date: January 30, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Takahiro KAWASAKI, Yukiteru MATSUI, Akifumi GAWASE
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Publication number: 20190283206Abstract: A polishing pad is described. The polishing pad includes a surface having plural recess portions, and a substrate is polished by the surface. In the pad, an average width of the recess portions at one area of the surface in a direction parallel to the surface is 20 ?m or less, and an average density of the recess portions at one area of the surface is 1,300/mm2 or more.Type: ApplicationFiled: August 22, 2018Publication date: September 19, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Takahiko KAWASAKI, Yukiteru MATSUI, Akifumi GAWASE
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Publication number: 20190259777Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.Type: ApplicationFiled: April 30, 2019Publication date: August 22, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yasuhito YOSHIMIZU, Akifumi GAWASE, Kei WATANABE, Shinya ARAI
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Patent number: 10319734Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.Type: GrantFiled: January 20, 2016Date of Patent: June 11, 2019Assignee: Toshiba Memory CorporationInventors: Yasuhito Yoshimizu, Akifumi Gawase, Kei Watanabe, Shinya Arai
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Patent number: 10283383Abstract: According to one embodiment, a planarization method and a planarization apparatus are provided. In the planarization method, a work surface of a work piece is planarized by bringing the work surface of the work piece containing a silicon oxide film and a surface of a solid plate onto which hydrogen ions are adsorbed, into contact or extremely close proximity with one another in a state in which a process liquid containing fluorine ions is supplied to the surface of the solid plate.Type: GrantFiled: August 14, 2015Date of Patent: May 7, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Akifumi Gawase, Yukiteru Matsui, Gaku Minamihaba, Hajime Eda
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Patent number: 10195716Abstract: According to one embodiment, a dresser includes a base metal plate, and a plurality of chip portions that are provided on the base metal plate. Each chip portion includes a Si substrate having a projection at an upper portion thereof and a diamond layer provided on the projection of the Si substrate.Type: GrantFiled: February 10, 2017Date of Patent: February 5, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takahiko Kawasaki, Yukiteru Matsui, Akifumi Gawase
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Patent number: 10121677Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes forming, on a substrate, protruding portions with first films on the surfaces thereof, respectively, forming a second film different from the first films so as to fill a depressed portion between the protruding portions and to cover the protruding portions, processing in such a manner that the top surface of the second film on the depressed portion is higher than the top surface of the second film on the protruding portions after forming the second film to cover the protruding portions, and polishing the second film on the depressed and protruding portions to expose the first films.Type: GrantFiled: January 6, 2016Date of Patent: November 6, 2018Assignee: Toshiba Memory CorporationInventors: Yukiteru Matsui, Takahiko Kawasaki, Akifumi Gawase, Kenji Iwade
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Publication number: 20180277388Abstract: A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a CMP method.Type: ApplicationFiled: May 30, 2018Publication date: September 27, 2018Applicant: Toshiba Memory CorporationInventors: Yukiteru MATSUI, Kyoichi SUGURO, Akifumi GAWASE, Takahiko KAWASAKI
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Patent number: 10079153Abstract: In a substrate processing method according to the embodiment, a first material is implanted into a surface of a target film to modify the surface of the target film. The surface of the target film is dissolved to remove the surface of the target film by bringing a catalytic material close to the surface of the target film or by contacting the catalytic material to the surface of the target film while supplying a process solution on the surface of the target film which has been modified.Type: GrantFiled: February 16, 2017Date of Patent: September 18, 2018Assignee: Toshiba Memory CorporationInventors: Akifumi Gawase, Yukiteru Matsui, Takahiko Kawasaki
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Patent number: 10010997Abstract: In accordance with an embodiment, a polishing method includes supplying slurry to a surface of a polishing layer including a polymer, and bringing a polishing object into contact with the polishing layer to polish the polishing object. The polishing layer has a fibrous first substance mixed therein or contains a second substance. The second substance is higher in specific heat and higher in thermal conductivity than the polymer in such a manner that the second substance is surrounded by the polymer.Type: GrantFiled: September 8, 2015Date of Patent: July 3, 2018Assignee: Toshiba Memory CorporationInventors: Akifumi Gawase, Yukiteru Matsui, Takahiko Kawasaki, Yosuke Otsuka, Hajime Eda
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Patent number: 10008390Abstract: A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a CMP method.Type: GrantFiled: March 10, 2015Date of Patent: June 26, 2018Assignee: Toshiba Memory CorporationInventors: Yukiteru Matsui, Kyoichi Suguro, Akifumi Gawase, Takahiko Kawasaki
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Publication number: 20180056482Abstract: According to one embodiment, a dresser includes a base metal plate, and a plurality of chip portions that are provided on the base metal plate. Each chip portion includes a Si substrate having a projection at an upper portion thereof and a diamond layer provided on the projection of the Si substrate.Type: ApplicationFiled: February 10, 2017Publication date: March 1, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Takahiko KAWASAKI, Yukiteru MATSUI, Akifumi GAWASE
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Publication number: 20180061654Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes bringing a first catalyst into contact with a workpiece to form an oxide film on a surface of the workpiece, and bringing a second catalyst different from the first catalyst and the oxide film into contact with each other or moving the second catalyst and the oxide film closer to each other to elute the oxide film into a treatment liquid.Type: ApplicationFiled: November 6, 2017Publication date: March 1, 2018Applicant: Toshiba Memory CorporationInventors: Akifumi Gawase, Yukiteru Matsui, Takahiko Kawasaki
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Patent number: 9837279Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes bringing a first catalyst into contact with a workpiece to form an oxide film on a surface of the workpiece, and bringing a second catalyst different from the first catalyst and the oxide film into contact with each other or moving the second catalyst and the oxide film closer to each other to elute the oxide film into a treatment liquid.Type: GrantFiled: March 10, 2016Date of Patent: December 5, 2017Assignee: Toshiba Memory CorporationInventors: Akifumi Gawase, Yukiteru Matsui, Takahiko Kawasaki