Patents by Inventor Akifumi Suzuki
Akifumi Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10908988Abstract: A storage apparatus includes: a controller; and a plurality of storage drives, wherein the controller issues a read command for specifying a value associated with an error correction mode to a first storage drive of the plurality of storage drives, the first storage drive selects the error correction mode associated with the value specified by the read command from a plurality of error correction modes, the plurality of error correction modes include a first error correction mode and a second error correction mode with a higher correcting capability and a longer maximum delay time than those of the first error correction mode, and the first storage drive executes a read of data from a storage medium in the selected error correction mode.Type: GrantFiled: April 3, 2017Date of Patent: February 2, 2021Assignee: Hitachi, Ltd.Inventors: Mitsuo Date, Hideyuki Koseki, Akifumi Suzuki, Masahiro Tsuruya
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Patent number: 10901401Abstract: Provided are a correlation determination unit to set, as a first apparatus, one apparatus among a plurality of apparatuses, set, as a first quality value, a quality value indicating a quality of an intermediate product processed by the first apparatus, set, as a second apparatus, an apparatus among the plurality of apparatuses that belongs to a process prior to the process to which the first apparatus belongs, set, as a second quality value, a quality value of an intermediate product processed by the second apparatus and determine whether correlation exists between the first quality value and the second quality value; a set determination unit to determine, using a quality standard value BQ indicating a standard of quality of the intermediate product, whether the first apparatus and the second apparatus are a set of apparatuses for which a first error between the first quality value and the quality standard value BQ and a second error between the second quality value and the quality standard value BQ cancel eaType: GrantFiled: January 15, 2016Date of Patent: January 26, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Mitsuteru Shiba, Akifumi Suzuki
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Patent number: 10896700Abstract: A system including a first storage drive and a superior device superior to the first storage drive, wherein the superior device specifies a first allowable environmental temperature that makes the remaining lifetime of the first storage drive longer than the remaining operation schedule period of the first storage drive, and controls an environmental temperature adjusting device that adjusts the environmental temperature of the first storage drive on the basis of the first allowable environmental temperature.Type: GrantFiled: April 19, 2017Date of Patent: January 19, 2021Assignee: HITACHI, LTD.Inventors: Masahiro Tsuruya, Masahiro Arai, Akifumi Suzuki, Shimpei Nomura
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Patent number: 10884630Abstract: A storage system includes a controller and a nonvolatile memory drive, in which the controller transmits a write request that designates a volume identifier of a volume to be provided to a host, to the nonvolatile memory drive; the nonvolatile memory drive exclusively allocates a free block selected from a plurality of blocks to the volume identifier; write data of the write request is written to the free block; when the write data is update write data, an area that stores data to be updated is changed to an invalid data area; and after valid data of a block including the invalid data area is migrated to another block, all data of the block including the invalid data area is erased.Type: GrantFiled: April 13, 2017Date of Patent: January 5, 2021Assignee: Hitachi, Ltd.Inventors: Koji Hosogi, Naoya Okada, Akifumi Suzuki, Hideyuki Koseki, Masahiro Tsuruya
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Publication number: 20200394256Abstract: A storage system that performs irreversible compression on time-series data using a compressor/decompressor based on machine learning calculates a statistical amount value of each of one or more kinds of statistical amounts based on one or more parameters in relation to original data (time-series data input to a compressor/decompressor) and calculates a statistical amount value of each of the one or more kinds of statistical amounts based on the one or more kinds of parameters in relation to decompressed data (time-series data output from the compressor/decompressor) corresponding to the original data. The machine learning of the compressor/decompressor is performed based on the statistical amount value calculated for each of the one or more kinds of statistical amounts in relation to the original data and the statistical amount value calculated for each of the one or more kinds of statistical amounts in relation to the decompressed data.Type: ApplicationFiled: March 18, 2020Publication date: December 17, 2020Inventors: Takahiro NARUKO, Hiroaki AKUTSU, Akifumi SUZUKI
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Patent number: 10860577Abstract: An intermediate device is disposed between a host and a search target. Search requests of m-multiplicity (requests involving a data transfer amount that is unknown to the host) for at least one among n-processes (n is an integer equal to or more than 1) to be executed by the host are issued as requests from the host to the intermediate device. A temporary area associated with the search requests is allocated in the host. For each of the search requests, the intermediate device recognizes a hit data volume in accordance with the search request within a search scope. For each of the search, the hit data is written in an area of the temporary area that corresponds to a write destination address. The write destination address is updated for each of the search requests on the basis of the recognized hit data volume.Type: GrantFiled: December 24, 2015Date of Patent: December 8, 2020Assignee: HITACHI, LTD.Inventors: Koji Hosogi, Akifumi Suzuki, Kazuyoshi Serizawa, Akira Yamamoto
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Patent number: 10838628Abstract: A storage system includes a flash storage in which a plurality of flash chips are accommodated and a storage controller that reads/writes data from and on the flash storage in response to a request from a high-order device, the flash chip capable of changing a mode of a cell of the flash chip to a first mode and a second mode in which an amount of storable information is less but a lifetime is longer than in the first mode, and a control method of the storage system is provided. The storage system includes: a prediction unit; a determination unit; and a mode change.Type: GrantFiled: August 31, 2018Date of Patent: November 17, 2020Assignee: HITACHI, LTD.Inventors: Akira Yamamoto, Akifumi Suzuki
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Publication number: 20200340089Abstract: To perform blast quenching for a plurality of solution-treated workpieces in a uniform manner for a group of the workpieces to allow the group of the workpieces to have a uniform quality, there is provided a quenching apparatus configured to perform quenching treatment on a solution-treated workpiece unloaded from a solution treatment furnace. The solution treatment furnace includes a plurality of workpiece storage chambers arranged horizontally into an annular shape and stacked in a vertical direction and a plurality of workpiece unloading ports corresponding to the workpiece storage chambers. The quenching apparatus is provided so as to be movable in accordance with the positions of the workpiece unloading ports.Type: ApplicationFiled: April 17, 2020Publication date: October 29, 2020Inventors: Akifumi SUZUKI, Hitoshi SAKAMOTO
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Patent number: 10803972Abstract: A flash memory module includes a flash memory and a controller. The controller acquires information indicating reliability of monitoring target data of the flash memory, specifies a first cell, which is a cell having a threshold voltage level lower than a threshold voltage level of a corresponding cell in expected value data obtained by correcting an error bit of the monitoring target data, among cells in which error bits have occurred of the monitoring target data when it is determined that the reliability indicated by the acquired information is lower than a predetermined condition, and transmits rewrite correction target cell data, which is data corresponding to data of the first cell in the expected value data, to the flash memory. The flash memory injects an electron into the first cell based on a threshold voltage indicated by the rewrite correction target cell data.Type: GrantFiled: March 6, 2017Date of Patent: October 13, 2020Assignee: Hitachi, Ltd.Inventors: Akifumi Suzuki, Junji Ogawa
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Publication number: 20200310655Abstract: Provided is a storage system that can store various types of and large amounts of sensor data while accurately compressing the sensor data without wasting storage resources. The storage system includes: a storage that records sensor data output from a plurality of sensors; a processor that controls recording of sensor data in the storage; and a memory that records parameters of the plurality of sensors. The processor reads parameters assigned to the sensors that output the sensor data from the memory, normalizes the sensor data based on the parameters, compresses the normalized sensor data, and records the compressed sensor data in the storage.Type: ApplicationFiled: March 5, 2020Publication date: October 1, 2020Inventors: Akifumi SUZUKI, Hiroaki AKUTSU, Takahiro NARUKO
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Publication number: 20200301595Abstract: An object of the invention is to optimize a storage cost for data. There is provided a storage system including a storage device, a memory, and a processor configured to control input and output of data to and from the storage device. The processor monitors a storage amount that is at least one of a write amount (a total amount of data received as a write target) and a physical use amount (a total amount of data physically stored in the storage device), and a read amount (a total amount of data that is read), and calculates a fee as a storage cost that is a cost related to use of the storage device in a target period, based on a storage amount and a read amount in the target period in accordance with a monitoring result.Type: ApplicationFiled: March 9, 2020Publication date: September 24, 2020Inventors: Hiroaki AKUTSU, Takahiro NARUKO, Akifumi SUZUKI
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Patent number: 10768838Abstract: When a logical capacity of a nonvolatile semiconductor memory is increased, after a logical capacity which is allocated to a RAID group but unused is released, the RAID group is reconfigured to include the released logical capacity and the increased logical capacity. When the logical capacity of the nonvolatile semiconductor memory is reduced, after the reduced logical capacity is released from the RAID group, the RAID group is reconfigured with the released logical capacity.Type: GrantFiled: January 12, 2017Date of Patent: September 8, 2020Assignee: HITACHI, LTD.Inventors: Shimpei Nomura, Masahiro Tsuruya, Akifumi Suzuki
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Patent number: 10725865Abstract: A storage unit includes a plurality of storage devices that form a RAID group, that are coupled to the same bus, and that communicate with each other. Each of the plurality of storage devices includes a device controller and a storage medium. The plurality of storage devices store each of data and parities generated on the basis of the data, the data and the parities being included in RAID stripes. A first device controller of a first storage device included in the RAID group transmits, to the plurality of storage devices included in the RAID group other than the first storage device, an instruction to transfer the data and/or the parities included in the RAID stripes and restores the data or the parity corresponding to the first storage device of the RAID stripes on the basis of the transferred data and the transferred parities.Type: GrantFiled: February 25, 2015Date of Patent: July 28, 2020Assignee: HITACHI LTD.Inventors: Mitsuhiro Okada, Akifumi Suzuki, Satoshi Morishita, Akira Yamamoto
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Patent number: 10635534Abstract: In technique for dividing ECC large in size, plural ECCs of different sizes are required to be managed and control over storage areas of NVM is intricate. In addition, a relatively reliable page (a minimum record unit) and a relatively unreliable page are determined beforehand depending upon which recording method is adopted. However, as dispersion exists in quality among NVMs, it may occur among NVMs that dispersion in an error bit count is great among pages of the same reliability. An NVM controller in a nonvolatile memory (NVM) module divides the ECCCW into N pieces (N: two or a larger integer) of ECCCW portions and records the N pieces of ECCCW portions in N pieces of storage areas out of plural storage areas in one or more NVMs configuring an NVM section.Type: GrantFiled: August 31, 2018Date of Patent: April 28, 2020Assignee: HITACHI, LTD.Inventors: Akifumi Suzuki, Shimpei Nomura, Yuto Kamo
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Patent number: 10552044Abstract: A management controller controls a data buffer and a flash controller, which controls I/O of data to and from flash memories, based on a search request. A data decompression engine includes a plurality of data decompression circuits for decompressing, in parallel, the compressed data transferred from the data buffer. A data search engine includes a plurality of data search circuits for searching, in parallel, data which satisfies search conditions among the respective data that were decompressed by the data decompression circuits, and transfers, to the search request source, the data obtained in the search performed by the data search circuits, wherein the flash controller reads, in parallel, a plurality of compressed data requested in the search request, and transfers the read compressed data to the data buffer, and the management controller transfers the compressed data to the data decompression engine when the compressed data is stored in the data buffer.Type: GrantFiled: March 27, 2014Date of Patent: February 4, 2020Assignee: Hitachi, Ltd.Inventors: Yoshiki Kurokawa, Satoru Watanabe, Yoshitaka Tsujimoto, Mitsuhiro Okada, Akifumi Suzuki
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Publication number: 20190361611Abstract: A storage system includes a controller and a nonvolatile memory drive, in which the controller transmits a write request that designates a volume identifier of a volume to be provided to a host, to the nonvolatile memory drive; the nonvolatile memory drive exclusively allocates a free block selected from a plurality of blocks to the volume identifier; write data of the write request is written to the free block; when the write data is update write data, an area that stores data to be updated is changed to an invalid data area; and after valid data of a block including the invalid data area is migrated to another block, all data of the block including the invalid data area is erased.Type: ApplicationFiled: April 13, 2017Publication date: November 28, 2019Inventors: Koji HOSOGI, Naoya OKADA, Akifumi SUZUKI, Hideyuki KOSEKI, Masahiro TSURUYA
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Patent number: 10467176Abstract: An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface.Type: GrantFiled: February 25, 2015Date of Patent: November 5, 2019Assignee: Hitachi, Ltd.Inventors: Satoshi Morishita, Mitsuhiro Okada, Akifumi Suzuki, Shimpei Nomura
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Patent number: 10459773Abstract: The PLD management system includes a PLD management unit that manages the usage status of each of one or more PLDs. The PLD management unit receives a PLD usage request from a request source module which is one of a plurality of processing modules sharing each of the one or more PLDs. when the PLD management unit receives the usage request, the PLD management unit performs control to prevent two or more processing modules including the request source module from utilizing the same PLD at the same time based on a current usage status of a PLD corresponding to the usage request and content of the usage request.Type: GrantFiled: May 19, 2016Date of Patent: October 29, 2019Assignee: HITACHI, LTD.Inventors: Mitsuhiro Okada, Akifumi Suzuki, Takayuki Suzuki, Yuichiro Aoki, Naoya Nishio
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Publication number: 20190278486Abstract: In a storage system capable of making connection to one or more SSDs and capable of controlling inputting and outputting of data to and from a storage region of the SSD, the storage system includes a processor that executes a process. The processor is configured to manage a part of a storage region provided by the one or more SSDs with the same characteristics as a first storage region (performance maintenance region) used to store predetermined data, determine data to be stored in the first storage region in data of which a write access frequency is less than a predetermined value, store the data in the first storage region, and store data determined not to be stored in the first storage region in a second storage region (a normal region) which is different from the first storage region and is provided by the one or SSDs with the same characteristics.Type: ApplicationFiled: August 2, 2018Publication date: September 12, 2019Applicant: HITACHI, LTD.Inventors: Takahiro Naruko, Masahiro Tsuruya, Akifumi Suzuki, Shimpei Nomura
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Publication number: 20190213078Abstract: A storage apparatus includes: a controller; and a plurality of storage drives, wherein the controller issues a read command for specifying a value associated with an error correction mode to a first storage drive of the plurality of storage drives, the first storage drive selects the error correction mode associated with the value specified by the read command from a plurality of error correction modes, the plurality of error correction modes include a first error correction mode and a second error correction mode with a higher correcting capability and a longer maximum delay time than those of the first error correction mode, and the first storage drive executes a read of data from a storage medium in the selected error correction mode.Type: ApplicationFiled: April 3, 2017Publication date: July 11, 2019Inventors: Mitsuo DATE, Hideyuki KOSEKI, Akifumi SUZUKI, Masahiro TSURUYA