Patents by Inventor Akifumi Tosa

Akifumi Tosa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11013068
    Abstract: A multilayer heating body (1) includes a ceramic substrate (3), an electrode (4), heaters (5, 7), terminals (11, 13, 15, 17), and an electricity supply path (19). Through vias which constitute the electricity supply path include at least one combination of through vias ?, ?, ?, and ? which meets the following conditions (1) and (2). Condition (1): when the ceramic substrate is viewed from the front surface (3a) side toward the back surface (3b) side, the through via ? is located at a position where the through via ? overlaps the through via ?, or in the vicinity of the through via ?. Condition (2): when the ceramic substrate is viewed from the front surface side toward the back surface side, the through via ? is located at a position between the through via ? and the through via ?, or located at a position where the through via ? overlaps the through via ?, or in the vicinity of the through via ?.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: May 18, 2021
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Akifumi Tosa, Yasuhiko Inui, Kaname Miwa, Yosuke Shinozaki
  • Publication number: 20170359859
    Abstract: A multilayer heating body (1) includes a ceramic substrate (3), an electrode (4), heaters (5, 7), terminals (11, 13, 15, 17), and an electricity supply path (19). Through vias which constitute the electricity supply path include at least one combination of through vias ?, ?, ?, and ? which meets the following conditions (1) and (2). Condition (1): when the ceramic substrate is viewed from the front surface (3a) side toward the back surface (3b) side, the through via ? is located at a position where the through via ? overlaps the through via ?, or in the vicinity of the through via ?. Condition (2): when the ceramic substrate is viewed from the front surface side toward the back surface side, the through via ? is located at a position between the through via ? and the through via ?, or located at a position where the through via ? overlaps the through via ?, or in the vicinity of the through via ?.
    Type: Application
    Filed: June 9, 2016
    Publication date: December 14, 2017
    Inventors: Akifumi TOSA, Yasuhiko INUI, Kaname MIWA, Yosuke SHINOZAKI
  • Patent number: 9136031
    Abstract: An alumina sintered body contains alumina as a main component and titanium. The alumina sintered body further contains at least one element selected from the group consisting of lanthanum, neodymium, and cerium. Aluminum is contained in the alumina sintered body in an amount such that a ratio of aluminum oxide to total oxides in the alumina sintered body becomes 93.00 to 99.85% by weight where the total oxides are defined as a total amount of all oxides contained in the alumina sintered body. Titanium is contained in an amount such that a ratio of titanium oxide to the total oxides becomes 0.10 to 2.00% by weight. Lanthanum, neodymium, and cerium are contained in a combined amount such that a ratio of the combined amount to the total oxides becomes 0.05 to 5.00% by weight. Volume resistivity is 1×105 to 1×1012 ?·cm at room temperature.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: September 15, 2015
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Yoichi Ito, Masaki Tsuji, Akifumi Tosa, Takenori Sawamura
  • Publication number: 20130285336
    Abstract: An alumina sintered body contains alumina as a main component and titanium. The alumina sintered body further contains at least one element selected from the group consisting of lanthanum, neodymium, and cerium. Aluminum is contained in the alumina sintered body in an amount such that a ratio of aluminum oxide to total oxides in the alumina sintered body becomes 93.00 to 99.85% by weight where the total oxides are defined as a total amount of all oxides contained in the alumina sintered body. Titanium is contained in an amount such that a ratio of titanium oxide to the total oxides becomes 0.10 to 2.00% by weight. Lanthanum, neodymium, and cerium are contained in a combined amount such that a ratio of the combined amount to the total oxides becomes 0.05 to 5.00% by weight. Volume resistivity is 1×105 to 1×1012 ?·cm at room temperature.
    Type: Application
    Filed: April 23, 2013
    Publication date: October 31, 2013
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Yoichi ITO, Masaki TSUJI, Akifumi TOSA, Takenori SAWAMURA
  • Patent number: 8071496
    Abstract: A silicon nitride-melilite composite sintered body in accordance with the invention includes silicon nitride and a melilite Me2Si3O3N4, where Me denotes a metal element combining with silicon nitride to generate the melilite. The silicon nitride-melilite composite sintered body contains Si in a range of 41 to 83 mole percent in Si3N4 equivalent and Me in a range of 13 to 50 mole percent in oxide equivalent. The silicon nitride-melilite composite sintered body has an average thermal expansion coefficient that is arbitrarily adjustable in a range of 2 to 6 ppm/K at temperatures of 23 to 150° C. The silicon nitride-melilite composite sintered body has a high Young's modulus, a high mechanical strength, and excellent sintering performance. A device used for inspection of semiconductor in accordance with the invention utilizes such a silicon nitride-melilite composite sintered body.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: December 6, 2011
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Yasushi Hara, Tetsuya Maeda, Akifumi Tosa, Takenori Sawamura
  • Patent number: 7956454
    Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: June 7, 2011
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Akifumi Tosa
  • Patent number: 7778010
    Abstract: A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: August 17, 2010
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Motohiko Sato, Kazuhiro Hayashi, Akifumi Tosa, Kenji Murakami, Tomohide Yamada, Motonobu Kurahashi
  • Publication number: 20100130345
    Abstract: A silicon nitride-melilite composite sintered body in accordance with the invention includes silicon nitride and a melilite Me2Si3O3N4, where Me denotes a metal element combining with silicon nitride to generate the melilite. The silicon nitride-melilite composite sintered body contains Si in a range of 41 to 83 mole percent in Si3N4 equivalent and Me in a range of 13 to 50 mole percent in oxide equivalent. The silicon nitride-melilite composite sintered body has an average thermal expansion coefficient that is arbitrarily adjustable in a range of 2 to 6 ppm/K at temperatures of 23 to 150° C. The silicon nitride-melilite composite sintered body has a high Young's modulus, a high mechanical strength, and excellent sintering performance. A device used for inspection of semiconductor in accordance with the invention utilizes such a silicon nitride-melilite composite sintered body.
    Type: Application
    Filed: November 11, 2009
    Publication date: May 27, 2010
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Yasushi HARA, Tetsuya Maeda, Akifumi Tosa, Takenori Sawamura
  • Publication number: 20090268373
    Abstract: A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.
    Type: Application
    Filed: July 2, 2009
    Publication date: October 29, 2009
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Motohiko SATO, Kazuhiro HAYASHI, Akifumi TOSA, Kenji MURAKAMI, Tomohide YAMADA, Motonobu KURAHASHI
  • Publication number: 20090255719
    Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.
    Type: Application
    Filed: June 1, 2009
    Publication date: October 15, 2009
    Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Akifumi Tosa
  • Patent number: 7573697
    Abstract: A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: August 11, 2009
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Motohiko Sato, Kazuhiro Hayashi, Akifumi Tosa, Kenji Murakami, Tomohide Yamada, Motonobu Kurahashi
  • Patent number: 7557440
    Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: July 7, 2009
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Akifumi Tosa
  • Patent number: 7362560
    Abstract: A multilayer electronic component including a multilayer ceramic capacitor is disclosed, which includes a laminate of dielectric layers and internal electrodes disposed on the dielectric layers; at least one via-conductor penetrating the dielectric layers and connecting to the internal electrodes; and at least one external terminal formed on an outer surface of the laminate and connecting to an end of the via-conductor, wherein the external terminal includes a lower bump formed on the outer surface of the laminate and an upper bump formed on the lower bump, and a diameter of the upper bump is smaller than that of the lower bump.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: April 22, 2008
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Yasuhiro Tsujimura, Akifumi Tosa, Motonobu Kurahashi, Manabu Sato
  • Patent number: 7233480
    Abstract: A laminated ceramic capacitor (10) divided into a first laminate (11), a second laminate (12), a third laminate (13), and a fourth laminate (14). The first laminate (11) includes a ceramic layer (15) serving as a dielectric layer. The ceramic layer (15) is thicker than a ceramic layer (17) sandwiched between internal electrodes (16a) in the second laminate (12) or the fourth laminate (14), and thinner than 20 times the thickness of the ceramic layer (17). The third laminate (13) includes dielectric layers, which serve as the ceramic layers (17), and has a thickness of 5% of the total thickness of the second laminate (12) and the fourth laminate (14). Accordingly, the third laminate (13) achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate (11), portions of via electrodes (18) that extend without being electrically connected to the internal electrodes (16b) can be shortened.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: June 19, 2007
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Kazuhiro Hayashi, Akifumi Tosa, Motohiko Sato, Jun Otsuka, Manabu Sato
  • Publication number: 20070045814
    Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.
    Type: Application
    Filed: August 24, 2006
    Publication date: March 1, 2007
    Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Akifumi Tosa
  • Publication number: 20070047175
    Abstract: A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 1, 2007
    Inventors: Motohiko Sato, Kazuhiro Hayashi, Akifumi Tosa, Kenji Murakami, Tomohide Yamada, Motonobu Kurahashi
  • Publication number: 20060245142
    Abstract: A laminated ceramic capacitor (10) divided into a first laminate (11), a second laminate (12), a third laminate (13), and a fourth laminate (14). The first laminate (11) includes a ceramic layer (15) serving as a dielectric layer. The ceramic layer (15) is thicker than a ceramic layer (17) sandwiched between internal electrodes (16a) in the second laminate (12) or the fourth laminate (14), and thinner than 20 times the thickness of the ceramic layer (17). The third laminate (13) includes dielectric layers, which serve as the ceramic layers (17), and has a thickness of 5% of the total thickness of the second laminate (12) and the fourth laminate (14). Accordingly, the third laminate (13) achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate (11), portions of via electrodes (18) that extend without being electrically connected to the internal electrodes (16b) can be shortened.
    Type: Application
    Filed: June 28, 2006
    Publication date: November 2, 2006
    Inventors: Kazuhiro Hayashi, Akifumi Tosa, Motohiko Sato, Jun Otsuka, Manabu Sato
  • Patent number: 7105070
    Abstract: A method for producing a ceramic substrate which employs a cofiring process using restraint sheets in which a second ceramic green sheet 7 is laminated on a green ceramic substrate 30 so as to cover surface conductors 32 of the green ceramic substrate 30, the second ceramic green sheet 7 subsequently being integrated with the green ceramic substrate 30. Restraint sheets 9, which are not sintered at a sintering temperature at which the green ceramic substrate 30 is sintered, are laminated on corresponding opposite sides of the green ceramic substrate 30 so as to restrain the green ceramic substrate 30 together with the second ceramic green sheet 7. The second ceramic green sheet 7 and the green ceramic substrate 30 are fired at a temperature at which the second ceramic green sheet 7 and the green ceramic substrate 30 are integrally sintered, whereas the restraint sheets 9 are not sintered, to thereby yield a ceramic substrate 40.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: September 12, 2006
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Akifumi Tosa, Jun Otsuka, Manabu Sato, Hisahito Kashima
  • Patent number: 7072169
    Abstract: A laminated ceramic capacitor 10 divided into a first laminate 11, a second laminate 12, a third laminate 13, and a fourth laminate 14. The first laminate 11 includes a ceramic layer 15 serving as a dielectric layer. The ceramic layer 15 is thicker than a ceramic layer 17 sandwiched between internal electrodes 16a in the second laminate 12 or the fourth laminate 14, and thinner than 20 times the thickness of the ceramic layer 17. The third laminate 13 includes dielectric layers, which serve as the ceramic layers 17, and has a thickness of 5% of the total thickness of the second laminate 12 and the fourth laminate 14. Accordingly, the third laminate 13 achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate 11, portions of via electrodes 18 that extend without being electrically connected to the internal electrodes 16b can be shortened.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: July 4, 2006
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Kazuhiro Hayashi, Akifumi Tosa, Motohiko Sato, Jun Otsuka, Manabu Sato
  • Patent number: 6995106
    Abstract: A dielectric ceramic material is represented by the following compositional formula, (100-a)[Bau{(ZnvCo1-v)wNbx}O?1]-a[MyTazO?2], where M represents at least one species selected from K, Na, and Li. In one method, the dielectric material is produced by mixing raw material powders such that proportions by mol of component metals simultaneously satisfy the relations, 0.5?a?25; 0.98?u?1.03; 0?v?1; 0.274?w?0.374; 0.646?x?0.696; 0.5?y?2.5; and 0.8?z?1.2. The method further includes subjecting the resultant mixture to primary pulverization; calcining the resultant powder at 1,100-1,300° C., followed by wet secondary pulverization; drying the resultant paste; granulating; molding the resultant granules to thereby yield a compact; and firing the compact in air advantageously at 1,400-1,600° C.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: February 7, 2006
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Takashi Oba, Masahiko Matsumiya, Akifumi Tosa, Kazuhisa Itakura