Patents by Inventor Akihiko Okutsu
Akihiko Okutsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10175338Abstract: A terminal device includes a reception unit configured to receive first and second electromagnetic waves and first and second sound waves; and a processor configured to determine first and second frequencies respectively indicating transmission frequencies of the first and second sound waves based on the first and second electromagnetic waves, and determine first and second beacons from which the first and second sound waves are transmitted, based on the determined first and second frequencies, wherein the processor determines a location of the terminal device based on the determined first and second beacons.Type: GrantFiled: December 2, 2015Date of Patent: January 8, 2019Assignee: FUJITSU LIMITEDInventor: Akihiko Okutsu
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Publication number: 20160202343Abstract: A terminal device includes a reception unit configured to receive first and second electromagnetic waves and first and second sound waves; and a processor configured to determine first and second frequencies respectively indicating transmission frequencies of the first and second sound waves based on the first and second electromagnetic waves, and determine first and second beacons from which the first and second sound waves are transmitted, based on the determined first and second frequencies, wherein the processor determines a location of the terminal device based on the determined first and second beacons.Type: ApplicationFiled: December 2, 2015Publication date: July 14, 2016Applicant: FUJITSU LIMITEDInventor: Akihiko OKUTSU
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Patent number: 9081050Abstract: A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.Type: GrantFiled: December 11, 2013Date of Patent: July 14, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Akihiko Okutsu, Hitoshi Saito, Yoshiaki Okano
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Publication number: 20140097861Abstract: A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Akihiko Okutsu, Hitoshi Saito, Yoshiaki Okano
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Patent number: 8633571Abstract: A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.Type: GrantFiled: May 29, 2012Date of Patent: January 21, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Akihiko Okutsu, Hitoshi Saito, Yoshiaki Okano
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Publication number: 20130015587Abstract: A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.Type: ApplicationFiled: May 29, 2012Publication date: January 17, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Akihiko Okutsu, Hitoshi Saito, Yoshiaki Okano
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Patent number: 6671271Abstract: A multiported integrated circuit performs pointer processing at the SONET STS and VT levels, and removes overhead information from a received electrical signal derived from an optical SONET signal. The integrated circuit operates to extract STM traffic and ATM traffic from the received SONET signal, in response to provisioning information received from a management and control unit. The extracted STM traffic is then combined with path switching information, and forwarded out a pair of interfaces, which enables path selection within an STM switch fabric within a local line unit and within a switch fabric on a partner line unit in an active/standby pair of line units. The path switching information is also output from the integrated circuit for transmission to a pair of ATM switch fabric units.Type: GrantFiled: June 3, 1999Date of Patent: December 30, 2003Assignee: Fujitsu Network Communications, Inc.Inventors: Takenao Takemura, Tri H. Doan, Akihiko Okutsu, Srinivas Pudu