Patents by Inventor Akihiko Takase
Akihiko Takase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7024487Abstract: In a communication network having a communication node connected to a plurality of service providers' networks, a network controller connected to the communication node, and a server for supplying network control information to the network controller, the server stores definition information of communication services provided by the service providers. When a service request specifying a communication path to be assured is received from the user terminal, the server retrieves communication service definition information matched with the service request and notifies the search result to the user terminal. In response to a notification of agreement from the user terminal, the server transmits network control information for setting a communication path to the network controller and the network controller supplies communication path control information generated on the basis of the network control information to the communication node.Type: GrantFiled: August 31, 2001Date of Patent: April 4, 2006Assignee: Hitachi, Ltd.Inventors: Misato Mochizuki, Akihiko Takase
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Patent number: 6993029Abstract: In a system in which communication is performed among a plurality of devices having a mechanism of disassembling a packet into ATM cells to send them and a plurality of devices having a mechanism of assembling the received ATM cells into the packet, a frame is prevented from being lost owing to change of virtual connections in the course of transferring the frame, improving reliability of the communication on the packet level. When the switch receives a request for change of switching, it does not processes that request at once, but confirms that the cell located at the boundary of the frame has been processed, before processing the change request, so as to protect the frame. When the switch receives a request for change of switching, it protects a frame by multicasting the cells to both destinations before change and after change, for a given period of time.Type: GrantFiled: February 19, 2003Date of Patent: January 31, 2006Assignee: Hitachi, Ltd.Inventors: Tetsuro Yoshimoto, Kazuho Miki, Akihiko Takase
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Patent number: 6980553Abstract: A router apparatus 5 is provided with an ATM switch, an IP controller for performing routing control as a controller for layer 3, plural kinds of interfaces which are individually provided to plural transmission paths in which various communications are performed, and a cell multiplexing/demultiplexing unit, and manages the cell communications between respective parts on the basis of identification information. The input packet is subjected to IP processing in an interface to be converted to a cell in a common format, and the cell is serially multiplexed with a cell from another interface on a cell basis, and transmitted to the ATM switch at the cell multiplexing/demultiplexing unit. Each interface and each cell multiplexing/demultiplexing unit sets and switches the identification information for the header portion of the packet and the cell to be communicated by using a table in which the corresponding relationship of the identification information is registered.Type: GrantFiled: May 23, 2002Date of Patent: December 27, 2005Assignee: Hitachi, Ltd.Inventors: Kazuho Miki, Masahiro Takatori, Akihiko Takase, Masaru Murakami, Koji Wakayama, Tetsuro Yoshimoto, Masao Kunimoto
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Publication number: 20050175351Abstract: An optical frequency division multiplexing network includes first optical communication paths connected to terminals, respectively, a second optical communication path connected to the outside and a node composed of a selection unit for selecting signals having optical frequencies to be sent to the plurality of terminals, respectively, from signals transmitted through the second optical communication path in optical frequency division multiplexing, a conversion unit for converting the selected signals into signals having a single optical frequency and an output unit for producing the converted signals to the temrinals through the first optical communication paths, respectively.Type: ApplicationFiled: July 21, 2003Publication date: August 11, 2005Inventors: Atsushi Takai, Ryoji Takeyari, Akihiko Takase
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Publication number: 20050008025Abstract: A router apparatus 5 is provided with an ATM switch, an IP controller for performing routing control as a controller for layer 3, plural kinds of interfaces which are individually provided to plural transmission paths in which various communications are performed, and a cell multiplexing/demultiplexing unit, and manages the cell communications between respective parts on the basis of identification information. The input packet is subjected to IP processing in an interface to be converted to a cell in a common format, and the cell is serially multiplexed with a cell from another interface on a cell basis, and transmitted to the ATM switch at the cell multiplexing/demultiplexing unit. Each interface and each cell multiplexing/demultiplexing unit sets and switches the identification information for the header portion of the packet and the cell to be communicated by using a table in which the corresponding relationship of the identification information is registered.Type: ApplicationFiled: July 20, 2004Publication date: January 13, 2005Inventors: Kazuho Miki, Masahiro Takatori, Akihiko Takase, Masaru Murakami, Koji Wakayama, Tetsuro Yoshimoto, Masao Kunimoto
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Publication number: 20040264460Abstract: A packet communication apparatus is provided having a receiving port which receives first packets. A switch, switches the first packets received at the receiving port. A first packet transform section, receives, through the switch section, the first packets received by the receiving port, and assembles the first packets into a second packet. A packet processing section processes the second packet transformed from the first packets by the first packet transform section. A second packet transform section disassembles the second packet, processed by the packet processing section, into the first packets and sends the first packets to the switch. A sending port receives the first packets sent from the second packet transform section through the switch, and sends the first packets.Type: ApplicationFiled: July 14, 2004Publication date: December 30, 2004Inventors: Tetsuro Yoshimoto, Kazuho Miki, Akihiko Takase
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Publication number: 20030206525Abstract: The cell output control apparatus includes a cell time slot allotment circuit for allotting, cells to be transmitted, to cell time slots with the cell transmission intervals changed, a first holder circuit for holding the value of ACR (Allowed Cell Rate), a first calculator circuit for calculating the ratio, LCR (Line Cell Rate)/ACR, a quantizer circuit for quantizing the ratio, LCR/ACR and controlling the allotment of cell time slots on the basis of the quantization error produced by the-quantization, a counter for counting the values of cell time slots, a second calculator circuit for calculating the cell time slots for cells, and a second holder circuit for holding the calculated results, whereby it is possible to absorb the quantization error produced when the ratio, LCR/ACR is quantized into an integral value.Type: ApplicationFiled: September 5, 2001Publication date: November 6, 2003Inventors: Kota Miyoshi, Takahiko Kozaki, Hajime Abe, Akihiko Takase
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Patent number: 6619865Abstract: An optical frequency division multiplexing network includes first optical communication paths connected to terminals, respectively, a second optical communication path connected to the outside and a node composed of a selection unit for selecting signals having optical frequencies to be sent to the plurality of terminals, respectively, from signals transmitted through the second optical communication path in optical frequency division multiplexing, a conversion unit for converting the selected signals into signals having a single optical frequency and an output unit for producing the converted signals to the terminals through the first optical communication paths, respectively.Type: GrantFiled: July 24, 1998Date of Patent: September 16, 2003Assignee: Hitachi, Ltd.Inventors: Atsushi Takai, Ryoji Takeyari, Akihiko Takase
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Publication number: 20030152085Abstract: In a system in which communication is performed among a plurality of devices having a mechanism of disassembling a packet into ATM cells to send them and a plurality of devices having a mechanism of assembling the received ATM cells into the packet, a frame is prevented from being lost owing to change of virtual connections in the course of transferring the frame, improving reliability of the communication on the packet level.Type: ApplicationFiled: February 19, 2003Publication date: August 14, 2003Inventors: Tetsuro Yoshimoto, Kazuho Miki, Akihiko Takase
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Publication number: 20030091049Abstract: This invention provides a network management equipment and a packet switching equipment which eliminate a connection setup delay time, reduce a delay and a delay variation involved in data transfer, and effectively perform connectionless data flow processing in a large data network. The network is divided into a connection-oriented core network and a plurality of connectionless access networks connected to the core network where a plurality of connections (called permanent virtual route (PVR)) are set up among a plurality of edge nodes. The network management equipment selects one route from a plurality of PVRs for connectionless data flow received from one of the access networks and transfers data along the PVR.Type: ApplicationFiled: November 1, 2002Publication date: May 15, 2003Inventors: Hajime Abe, Kazuho Miki, Noboru Endo, Akihiko Takase, Yoshito Sakurai
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Patent number: 6526045Abstract: In a system in which communication is performed among a plurality of devices having a mechanism of disassembling a packet into ATM cells to send them and a plurality of devices having a mechanism of assembling the received ATM cells into the packet, a frame is prevented from being lost owing to change of virtual connections in the course of transferring the frame, improving reliability of the communication on the packet level. When the switch receives a request for change of switching, it does not processes that request at once, but confirms that the cell located at the boundary of the frame has been processed, before processing the change request, so as to protect the frame. When the switch receives a request for change of switching, it protects a frame by multicasting the cells to both destinations before change and after change, for a given period of time.Type: GrantFiled: February 2, 2001Date of Patent: February 25, 2003Assignee: Hitachi, Ltd.Inventors: Tetsuro Yoshimoto, Kazuho Miki, Akihiko Takase
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Patent number: 6512745Abstract: This invention provides a network management equipment and a packet switching equipment which eliminate a connection setup delay time, reduce a delay and a delay variation involved in data transfer, and effectively perform connectionless data flow processing in a large data network. The network is divided into a connection-oriented core network and a plurality of connectionless access networks connected to the core network where a plurality of connections (called permanent virtual route (PVR)) are set up among a plurality of edge nodes. The network management equipment selects one route from a plurality of PVRs for connectionless data flow received from one of the access networks and transfers data along the PVR.Type: GrantFiled: October 1, 1999Date of Patent: January 28, 2003Assignee: Hitachi, Ltd.Inventors: Hajime Abe, Kazuho Miki, Noboru Endo, Akihiko Takase, Yoshito Sakurai
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Publication number: 20030005148Abstract: In a communication network having a communication node connected to a plurality of service providers' networks, a network controller connected to the communication node, and a server for supplying network control information to the network controller, the server stores definition information of communication services provided by the service providers. When a service request specifying a communication path to be assured is received from the user terminal, the server retrieves communication service definition information matched with the service request and notifies the search result to the user terminal. In response to a notification of agreement from the user terminal, the server transmits network control information for setting a communication path to the network controller and the network controller supplies communication path control information generated on the basis of the network control information to the communication node.Type: ApplicationFiled: August 31, 2001Publication date: January 2, 2003Inventors: Misato Mochizuki, Akihiko Takase
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Patent number: 6463066Abstract: Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.Type: GrantFiled: March 5, 2001Date of Patent: October 8, 2002Assignee: Hitachi, Ltd.Inventors: Norihiko Moriwaki, Kenichi Sakamoto, Akihiko Takase, Akio Makimoto, Kazumasa Yanagisawa
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Publication number: 20020136244Abstract: A router apparatus 5 is provided with an ATM switch, an IP controller for performing routing control as a controller for layer 3, plural kinds of interfaces which are individually provided to plural transmission paths in which various communications are performed, and a cell multiplexing/demultiplexing unit, and manages the cell communications between respective parts on the basis of identification information. The input packet is subjected to IP processing in an interface to be converted to a cell in a common format, and the cell is serially multiplexed with a cell from another interface on a cell basis, and transmitted to the ATM switch at the cell multiplexing/demultiplexing unit. Each interface and each cell multiplexing/demultiplexing unit sets and switches the identification information for the header portion of the packet and the cell to be communicated by using a table in which the corresponding relationship of the identification information is registered.Type: ApplicationFiled: May 23, 2002Publication date: September 26, 2002Inventors: Kazuho Miki, Masahiro Takatori, Akihiko Takase, Masaru Murakami, Koji Wakayama, Tetsuro Yoshimoto, Masao Kunimoto
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Patent number: 6424662Abstract: A router apparatus 5 is provided with an ATM switch, an IP controller for performing routing control as a controller for layer 3, plural kinds of interfaces which are individually provided to plural transmission paths in which various communications are performed, and a cell multiplexing/demultiplexing unit, and manages the cell communications between respective parts on the basis of identification information. The input packet is subjected to IP processing in an interface to be converted to a cell in a common format, and the cell is serially multiplexed with a cell from another interface on a cell basis, and transmitted to the ATM switch at the cell multiplexing/demultiplexing unit. Each interface and each cell multiplexing/demultiplexing unit sets and switches the identification information for the header portion of the packet and the cell to be communicated by using a table in which the corresponding relationship of the identification information is registered.Type: GrantFiled: February 4, 2000Date of Patent: July 23, 2002Assignee: Hitachi, Ltd.Inventors: Kazuho Miki, Masahiro Takatori, Akihiko Takase, Masaru Murakami, Koji Wakayama, Tetsuro Yoshimoto, Masao Kunimoto
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Patent number: 6385171Abstract: An LAN interface unit and an ATM switch unit cooperate to perform traffic control. A QoS unit monitors circumstances of an input buffer from a multiplexer of the ATM switch by means of a system controller and when an overflow of the input buffer is expected, the LAN interface unit of the multiplexer is instructed to perform traffic control. The LAN interface unit performs traffic control such as limitation of ATM cells inputted in the ATM switch.Type: GrantFiled: October 1, 1999Date of Patent: May 7, 2002Assignee: Hitachi, Ltd.Inventors: Akihiko Takase, Masahiro Takatori, Kazuho Miki, Masaru Murakami, Koji Wakayama, Tetsuro Yoshimoto, Masao Kunimoto
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Patent number: 6330227Abstract: The cell output control apparatus includes a cell time slot allotment circuit for allotting, cells to be transmitted, to cell time slots with the cell transmission intervals changed, a first holder circuit for holding the value of ACR (Allowed Cell Rate), a first calculator circuit for calculating the ratio, LCR (Line Cell Rate)/ACR, a quantizer circuit for quantizing the ratio, LCR/ACR and controlling the allotment of cell time slots on the basis of the quantization error produced by the quantization, a counter for counting the values of cell time slots, a second calculator circuit for calculating the cell time slots for cells, and a second holder circuit for holding the calculated results, whereby it is possible to absorb the quantization error produced when the ratio, LCR/ACR is quantized into an integral value.Type: GrantFiled: August 25, 1999Date of Patent: December 11, 2001Assignee: Hitachi, Ltd.Inventors: Kota Miyoshi, Takahiko Kozaki, Hajime Abe, Akihiko Takase
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Patent number: 6304555Abstract: In a system in which communication is performed among a plurality of devices having a mechanism of disassembling a packet into ATM cells to send them and a plurality of devices having a mechanism of assembling the received ATM cells into the packet, a frame is prevented from being lost owing to change of virtual connections in the course of transferring the frame, improving reliability of the communication on the packet level. When the switch receives a request for change of switching, it does not processes that request at once, but confirms that the cell located at the boundary of the frame has been processed, before processing the change request, so as to protect the frame. When the switch receives a request for change of switching, it protects a frame by multicasting the cells to both destinations before change and after change, for a given period of time.Type: GrantFiled: December 24, 1997Date of Patent: October 16, 2001Assignee: Hitachi, Ltd.Inventors: Tetsuro Yoshimoto, Kazuho Miki, Akihiko Takase
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Publication number: 20010028653Abstract: Upon initialization, a VPC is set up between edge nodes. A control processor of each node creates an IP address/VPC mapping table using IP routing information and an address mapping table mapping correspondence between IP addresses and ATM addresses and supplied by a network management system. A gateway assigns a VCC to each packet input to the network. A sending-side edge node inputs the packet to the VPC corresponding to its destination by referring to the IP address/VPC mapping table. A transit node performs packet switching over VP. A receiving-side edge node transfers each packet to the gateway corresponding to its destination. If a series of packets meet a predetermined condition in a given edge node, its control processor sends VCC information to input interfaces of the edge node so that the packets are switched by an ATM switch in the edge node without intervention of the control processor.Type: ApplicationFiled: June 14, 2001Publication date: October 11, 2001Inventors: Noboru Endo, Akihiko Takase, Hajime Abe, Kazuho Miki