Abstract: A system semiconductor device includes a system LSI cell portion and a global wiring layer. The system LSI cell portion has a plurality of functional blocks for realizing specific functions on a semiconductor chip. The global wiring layer has a wiring layer on a semiconductor substrate. The system LSI cell portion is laminated with the global wiring layer.

Abstract: A system semiconductor device includes a system LSI cell portion and a global wiring layer. The system LSI cell portion has a plurality of functional blocks for realizing specific functions on a semiconductor chip. The global wiring layer has a wiring layer on a semiconductor substrate. The system LSI cell portion is laminated with the global wiring layer.

Abstract: A system semiconductor device includes a system LSI cell portion and a global wiring layer. The system LSI cell portion has a plurality of functional blocks for realizing specific functions on a semiconductor chip. The global wiring layer has a wiring layer on a semiconductor substrate. The system LSI cell portion is laminated with the global wiring layer.

Abstract: In a semiconductor package stack module, an LSI (Large Scale Integrated circuit) is mounted, via fine bumps, on a ceramic carrier substrate or a flexible carrier film on which wiring conductors are formed. After a seal resin has been injected, the chip is thinned by, e.g., grinding. A plurality of such carrier substrates or carrier films are connected to each other by bumps via through holes which are electrically connected to the wiring conductors, thereby completing a tridimensional stack module. The module achieves a miniature, thin, dense, low cost, and reliable structure without resorting to a wire bonding system or a TAB (Tape Automated Bonding) system. In addition, the module has a minimum of wiring length and a desirable electric characteristic.

Abstract: A multichip module comprises a substrate mounting a plurality of circuit chips, a cover plate positioned over the circuit chips, and at least one pillar member for fixing the cover plate to the substrate to support it. The substrate has a plurality of circuit chips fixed in a predetermined pattern of locations on a side thereof. At least one pillar member fixes the cover plate to the substrate such that the cover plate is positioned over the circuit chips. Since the pillar member is fixed to the substrate at a small area to support the cover plate, the substrate can be prevented from deforming due to a temperature change. In order to secure the covering member, the pillar member is preferably fixed by means of an adhesive, a fit, or screwing.

Abstract: A chip tester for holding a semiconductor chip bonded via convex electrodes to a flexible substrate. The tester has a carrier body with a flat surface in contact with the flexible board. The carrier body overlies the flexible substrate so as to press down the flexible substrate. The tester also has a chip plate that underlies and contacts the semiconductor chip so as to urge the semiconductor chip toward the flexible substrate. At least a flat contact surface of the chip plate is made of an elastic material with a high elastic coefficient to obtain an adhesion with the semiconductor chip to prevent lateral displacement of the semiconductor chip. The tester also has a chip plate holder that underlies the flexible substrate and is positioned around both the semiconductor chip and the chip plate. The chip plate holder is spaced apart from the semiconductor chip so that the chip plate holder sandwiches the flexible substrate in cooperation with the carrier body.

Abstract: A multilayer wiring substrate which includes a plurality of laminated wiring layers, a plurality of insulating layers for providing insulation between the wiring layers, and a plurality of hollows provided within at least one of the insulating layers.

Abstract: In a wired substrate, a conductive pattern is formed of an alloy of gold, a base metal, and a noble metal and is contiguous to an insulating layer of a mixture of oxides of the base and the noble metals. The alloy preferably includes the base and the noble metals to a total amount of 0.2 to 2 percent by weight. More preferably, the base metal is titanium, aluminum, or copper. The noble metal is palladium, ruthenium, rhodium, or nickel. The wired substrate is manfactured by forming a first layer of the base metal, a second layer of the noble metal, and a selectively formed gold layer successively on the substrate and by heat treating at least the first, the second, and the gold layers to convert the gold layer and those portions of the first and the second layers on which the gold layer is formed, to the conductive pattern and to concurrently convert other portions of the first and the second layers to the insulating layer. The first, the second, and the gold layers are preferably 0.025 to 0.4, 0.025 to 0.

Abstract: A multi-layer comprising a multi-layer glass ceramic substrate and a multi-layer wire line matrix. The multi-layer wired line matrix includes an insulating layer made from a photosensitive insulating layer, amenable to time geometry processing. The insulating layer of the multi-layer wire line matrix has a pad for accommodating variations of the locations of the through holes. The metal is plated in and fills the through holes so that the metal is not cut off at the corners. The wire line matrix is composed of a plurality of layers of a photo-lithographically formed fine conductive pattern. The glass ceramic insulating layer is also formed photo-lithographically, and is formed of the source material of the insulating layers.

Abstract: A multi-layer comprising a multi-layer glass ceramic substrate and a multi-layer wire line matrix. The multi-layer wired line matrix includes an insulating layer made from a photosensitive insulating layer, amenable to time geometry processing. The insulating layer of the multi-layer wire line matrix has a pad for accommodating variations of the locations of the through holes. The metal is plated in and fills the through holes so that the metal is not cut off at the corners. The wire line matrix is composed of a plurality of layers of a photo-lithographically formed fine conductive pattern. The glass ceramic insulating layer is also formed photo-lithographically, and is formed of the source material of the insulating layers.

Abstract: In a wired substrate, a conductive pattern is formed of an alloy of gold, a base matal, and a noble metal and is contiguous to an insulating layer of a mixture of oxides of the base and the noble metals. The alloy preferably includes the base and the noble metals to a total amount of 0.2 to 2 percent by weight. More preferably, the base metal is titanium, aluminium, or copper. The noble metal is palladium, ruthenium, rhodium, or nickel. The wired substrate is manufactured by forming a first layer of the base metal, a second layer of the noble metal, and a selectively formed gold layer successively on the substrate and by heat treating at least the first, the second, and the gold layers to convert the gold layer and those portions of the first and the second layers on which the gold layer is formed, to the conductive pattern and to concurrently convert other portions of the first and the second layers to the insulating layer. The first, the second, and the gold layers are preferably 0.025 to 0.4, 0.025 to 0.

Abstract: A multilayer circuit construction includes a conductive layer formed of an alloy of a noble metal and a small amount of a base metal disposed on a heat resistant insulating substrate. The portion of the substrate not covered with the conductive alloy is covered with an oxide of the base metal constituent of the alloy. The construction may be formed by depositing a base metal layer over the substrate, followed by depositing the noble metal over a part of the base metal layer. By oxidizing at high temperatures, the exposed base metal layer is converted to oxide, while the noble metal and the base metal thereunder diffuse into each other to form the alloy.