Patents by Inventor Akihiro Funyu
Akihiro Funyu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8111575Abstract: There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.Type: GrantFiled: January 8, 2010Date of Patent: February 7, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Kaoru Mori, Shinya Fujioka, Yoshitaka Takahashi, Jun Ohno, Akihiro Funyu, Shinichiro Suzuki
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Publication number: 20100110818Abstract: There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.Type: ApplicationFiled: January 8, 2010Publication date: May 6, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Kaoru MORI, Shinya Fujioka, Yoshitaka Takahashi, Jun Ohno, Akihiro Funyu, Shinichiro Suzuki
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Patent number: 7471585Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.Type: GrantFiled: August 24, 2006Date of Patent: December 30, 2008Assignee: Fujitsu LimitedInventors: Naoharu Shinozaki, Tatsuya Kanda, Takahiko Sato, Akihiro Funyu
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Publication number: 20060285413Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.Type: ApplicationFiled: August 24, 2006Publication date: December 21, 2006Inventors: Naoharu Shinozaki, Tatsuya Kanda, Takahiko Sato, Akihiro Funyu
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Patent number: 7114025Abstract: A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.Type: GrantFiled: October 21, 2003Date of Patent: September 26, 2006Assignee: Fujitsu LimitedInventors: Tatsuya Kanda, Akihiro Funyu, Takahiko Sato, Yoshiaki Okuyama, Jun Ohno, Hitoshi Ikeda
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Patent number: 7113441Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.Type: GrantFiled: February 15, 2005Date of Patent: September 26, 2006Assignee: Fujitsu LimitedInventors: Naoharu Shinozaki, Tatsuya Kanda, Takahiko Sato, Akihiro Funyu
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Publication number: 20050146968Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.Type: ApplicationFiled: February 15, 2005Publication date: July 7, 2005Inventors: Naoharu Shinozaki, Tatsuya Kanda, Takahiko Sato, Akihiro Funyu
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Publication number: 20040199717Abstract: A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.Type: ApplicationFiled: October 21, 2003Publication date: October 7, 2004Applicant: FUJITSU LIMITEDInventors: Tatsuya Kanda, Akihiro Funyu, Takahiko Sato, Yoshiaki Okuyama, Jun Ohno, Hitoshi Ikeda
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Patent number: 6735141Abstract: A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.Type: GrantFiled: July 31, 2001Date of Patent: May 11, 2004Assignee: Fujitsu LimitedInventors: Hitoshi Ikeda, Akihiro Funyu, Shinya Fujioka, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato
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Patent number: 6724675Abstract: A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.Type: GrantFiled: January 29, 2003Date of Patent: April 20, 2004Assignee: Fujitsu LimitedInventors: Akihiro Funyu, Shinya Fujioka, Hitoshi Ikeda, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato, Yasurou Matsuzaki
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Publication number: 20030115405Abstract: A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.Type: ApplicationFiled: January 29, 2003Publication date: June 19, 2003Applicant: Fujitsu LimitedInventors: Akihiro Funyu, Shinya Fujioka, Hitoshi Ikeda, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato, Yasurou Matsuzaki
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Patent number: 6535950Abstract: A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.Type: GrantFiled: March 29, 2000Date of Patent: March 18, 2003Assignee: Fujitsu LimitedInventors: Akihiro Funyu, Shinya Fujioka, Hitoshi Ikeda, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato, Yasurou Matsuzaki
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Patent number: 6496433Abstract: A semiconductor device has a normal mode and a test mode for testing the semiconductor device, and is provided with a first circuit which receives an input signal, a test signal and an output enable signal, and outputs the input signal in response to the output enable signal, a second circuit which is coupled to the first circuit and outputs the input signal obtained from the first circuit, and power supply pads which receive a power supply voltage which is supplied in common to the first circuit and the second circuit. The first circuit fixes an output impedance of the second circuit to a high-impedance regardless of the output enable signal when the test signal indicates the test mode.Type: GrantFiled: January 9, 2001Date of Patent: December 17, 2002Assignee: Fujitsu LimitedInventors: Yasuhiro Okumura, Yoshitaka Takahashi, Akihiro Funyu
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Patent number: 6452453Abstract: The constant-current generator comprises a bias transistor whose drain and gate are connected to each other, and an outputting transistor. The threshold voltage of the outputting transistor is smaller than that of the bias transistor. The outputting transistor has the same source voltage and the same gate voltage as those of the bias transistor. Therefore, the gate-to-source voltages of the outputting transistor and the bias transistor are always kept equal. On the other hand, the drain-to-source current of the outputting transistor becomes larger than that of the bias transistor in accordance with the difference between the threshold voltages of the outputting transistor and the bias transistor. Accordingly, the outputting transistor can output a stable drain-to-source current even when the drain voltage of the bias transistor has shifted to lower the gate-to-source voltage thereof.Type: GrantFiled: May 1, 2000Date of Patent: September 17, 2002Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Akihiro Funyu
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Patent number: 6404688Abstract: A semiconductor memory device having a self-refresh operation includes a first circuit generating a first signal that specifies a first self-refresh cycle by a non-volatile circuit element provided in the semiconductor memory device, a second circuit receiving a second signal that specifies a second self-refresh cycle via a terminal that is used in common to another signal, and a third circuit generating a pulse signal having one of the first and second self-refresh cycles, the pulse signal being related to the self-refresh operation.Type: GrantFiled: February 26, 2001Date of Patent: June 11, 2002Assignee: Fujitsu LimitedInventors: Yoshiaki Okuyama, Yoshitaka Takahashi, Shinya Fujioka, Akihiro Funyu
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Patent number: 6396758Abstract: A semiconductor memory device having a self-refresh operation includes a detection circuit generating a detection signal when detecting a change of a given input signal, and a comparator circuit comparing the detection signal with a refresh request signal internally generated and generating a control signal indicative of a circuit operation.Type: GrantFiled: February 27, 2001Date of Patent: May 28, 2002Assignee: Fujitsu LimitedInventors: Hitoshi Ikeda, Tatsuya Kanda, Yoshitaka Takahashi, Shinya Fujioka, Akihiro Funyu
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Patent number: 6353561Abstract: A semiconductor memory device, such as a synchronous DRAM, receives external commands and an external clock signal via input buffers. The device generates internal clock signals having a slower frequency than the external clock signal and uses the internal clock signals to acquire the external command. This allows more than one external command to be acquired for each cycle of the external clock. The acquired external commands are provided to command decoders for decoding. A mask circuit is connected to the decoder circuits and inhibits the decoding circuits, except for a first one of the decoding circuits, from decoding the external commands for a predetermined time period, when the first decoder circuit is decoding the external commands.Type: GrantFiled: September 17, 1999Date of Patent: March 5, 2002Assignee: Fujitsu LimitedInventors: Akihiro Funyu, Shinya Fujioka, Yasuharu Sato, Toshiya Uchida
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Publication number: 20020024847Abstract: A semiconductor device includes a plurality of word lines selectable in a predetermined mode, and a circuit that precharges the plurality of word lines selected in the predetermined mode in a time division manner.Type: ApplicationFiled: August 15, 2001Publication date: February 28, 2002Applicant: FUJITSU LIMITEDInventors: Katsuhiro Mori, Shinya Fujioka, Akihiro Funyu
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Publication number: 20020006071Abstract: A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.Type: ApplicationFiled: July 31, 2001Publication date: January 17, 2002Applicant: Fujitsu LimitedInventors: Hitoshi Ikeda, Akihiro Funyu, Shinya Fujioka, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato
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Patent number: 6292426Abstract: A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.Type: GrantFiled: March 21, 2000Date of Patent: September 18, 2001Assignee: Fujitsu LimitedInventors: Hitoshi Ikeda, Akihiro Funyu, Shinya Fujioka, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato