Patents by Inventor Akihiro Hachigo

Akihiro Hachigo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8349078
    Abstract: The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm?2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 8, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Yu Saitoh, Kazuhide Sumiyoshi, Akihiro Hachigo, Makoto Kiyama, Seiji Nakahata
  • Patent number: 8283694
    Abstract: A GaN substrate on which an epitaxially grown layer of good quality can be formed is obtained. A GaN substrate as a group III nitride substrate has a surface in which the number of chlorine atoms per square centimeter of the surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013, wherein a plane orientation of the surface is any of a (0001) plane, a (11-20) plane, a (10-12) plane, a (10-10) plane, a (20-21) plane, a (10-11) plane, a (11-21) plane, a (11-22) plane, and a (11-24) plane of a wurtzite structure.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 9, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Publication number: 20120205661
    Abstract: A semiconductor device includes a supporting substrate, a conductive layer placed on the supporting substrate, and at least one group III nitride semiconductor layer placed on the conductive layer. Of the group III nitride semiconductor layers, a conductive-layer-neighboring group III nitride semiconductor layer has n type conductivity, dislocation density of at most 1×107 cm?2, and oxygen concentration of at most 5×1018 cm?3. Thus, an n-down type device having a semiconductor layer of high crystallinity can be provided.
    Type: Application
    Filed: January 19, 2012
    Publication date: August 16, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi KYONO, Kuniaki Ishihara, Akihiro Hachigo, Takahisa Yoshida, Masaki Ueno, Makoto Kiyama
  • Publication number: 20120208355
    Abstract: A gallium nitride substrate comprising a primary surface, the primary surface being tilted at an angle in a range of 20 to 160 degrees with respect to a C-plane of the substrate, and the substrate having a fracture toughness of more than or equal to 1.36 MN/m3/2.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 16, 2012
    Inventor: Akihiro HACHIGO
  • Patent number: 8183668
    Abstract: A gallium nitride substrate comprising a primary surface, the primary surface being tilted at an angle in a range of 20 to 160 degrees with respect to a C-plane of the substrate, and the substrate having a fracture toughness of more than or equal to 1.36 MN/m3/2.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: May 22, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Akihiro Hachigo
  • Patent number: 8177911
    Abstract: A method of evaluating damage of a compound semiconductor member, comprising: a step of performing measurement of photoluminescence on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a half width of a peak at a wavelength corresponding to a bandgap of the compound semiconductor member, in an emission spectrum obtained by the measurement of photoluminescence.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: May 15, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akihiro Hachigo, Takayuki Nishiura
  • Publication number: 20120104556
    Abstract: The present power device includes a metal-made support substrate, and a group III nitride conductive layer, a group III nitride active layer and an electrode successively formed on one main surface side of the metal-made support substrate. In addition, the present method for manufacturing a power device includes the steps of preparing a conductive-layer-joined metal-made support substrate in which a group III nitride conductive layer is joined to a metal-made support substrate, forming a group III nitride active layer on the group III nitride conductive layer, and forming an electrode on the group III nitride active layer. Thus, an inexpensive power device low in on-resistance and a method for manufacturing the same can be provided.
    Type: Application
    Filed: October 27, 2010
    Publication date: May 3, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Makoto KIYAMA, Hiromu SHIOMI, Kazuhide SUMIYOSHI, Akihiro HACHIGO
  • Publication number: 20120100643
    Abstract: A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength corresponding to a bandgap of the compound semiconductor member, in a spectrum of an optical constant obtained by the spectroscopic ellipsometry measurement.
    Type: Application
    Filed: January 3, 2012
    Publication date: April 26, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Akihiro Hachigo, Takayuki Nishiura, Keiji Ishibashi
  • Publication number: 20120094473
    Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate (1) is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface (3) is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface (3) is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface (3) is not more than 3×1013, and a haze level of the surface (3) is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface (3) is not more than 2×1014, and a haze level of the surface (3) is not more than 5 ppm.
    Type: Application
    Filed: December 23, 2011
    Publication date: April 19, 2012
    Inventors: Keiji ISHIBASHI, Akihiro HACHIGO, Masato IRIKURA, Seiji NAKAHATA
  • Patent number: 8143140
    Abstract: There is provided a method of producing a thin GaN film-joined substrate, including the steps of: joining on a GaN bulk crystalline body a substrate different in type or chemical composition from GaN; and dividing the GaN bulk crystalline body at a plane having a distance of at least 0.1 ?m and at most 100 ?m from an interface thereof with the substrate different in type, to provide a thin film of GaN on the substrate different in type, wherein the GaN bulk crystalline body had a surface joined to the substrate different in type, that has a maximum surface roughness Rmax of at most 20 ?m. Thus a GaN-based semiconductor device including a thin GaN film-joined substrate including a substrate different in type and a thin film of GaN joined firmly on the substrate different in type, and at least one GaN-based semiconductor layer deposited on the thin film of GaN, can be fabricated at low cost.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: March 27, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hitoshi Kasai, Akihiro Hachigo, Yoshiki Miura, Katsushi Akita
  • Patent number: 8124498
    Abstract: The present method of manufacturing a group III nitride semiconductor layer bonded substrate includes the steps of: implanting ions I of at least any of hydrogen and helium in a region having a prescribed depth D from one main surface of a group III nitride semiconductor substrate; bonding a different-composition substrate with the main surface of the group III nitride semiconductor substrate; obtaining a group III nitride semiconductor layer bonded substrate by separating the group III nitride semiconductor substrate at a region implanted with the ions I; and annealing the group III nitride semiconductor layer bonded substrate at a temperature not lower than 700° C. in an atmosphere of a nitrogen-containing gas N. Thus, a group III nitride semiconductor layer bonded substrate high in crystallinity of a group III nitride semiconductor layer is provided.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: February 28, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Akihiro Hachigo
  • Patent number: 8115927
    Abstract: A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength corresponding to a bandgap of the compound semiconductor member, in a spectrum of an optical constant obtained by the spectroscopic ellipsometry measurement.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: February 14, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akihiro Hachigo, Takayuki Nishiura, Keiji Ishibashi
  • Patent number: 8101968
    Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface is not more than 3×1013, and a haze level of the surface is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×1014, and a haze level of the surface is not more than 5 ppm.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: January 24, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Publication number: 20110315997
    Abstract: The present invention makes available a GaN substrate, and a method of its manufacture, that, with minimal machining allowances, facilitates consistent machining, and makes available a method of manufacturing a GaN layer-bonded substrate, and a semiconductor device, utilizing the GaN substrate.
    Type: Application
    Filed: November 13, 2009
    Publication date: December 29, 2011
    Applicant: Sumitomo Electric Industries Ltd.
    Inventor: Akihiro Hachigo
  • Publication number: 20110272734
    Abstract: The present invention is a minimal-defect light-emitting device substrate that enables emitted light to issue from a device's substrate side, and is a light-emitting device 100 substrate furnished with a transparent substrate 10 that is transparent to light of wavelengths between 400 nm and 600 nm, inclusive, and a nitride-based compound semiconductor thin film 1c formed onto one of the major surfaces of the transparent substrate 10 by a join. Letting the thermal expansion coefficient of the transparent substrate along a direction perpendicular to the major surface of the transparent substrate be ?1, and the thermal expansion coefficient of the nitride-based compound semiconductor thin film be ?2, then (?1??2)/?2 is between ?0.5 and 1.0, inclusive, and at up to 1200° C. the transparent substrate does not react with the nitride-based compound semiconductor thin film 1c.
    Type: Application
    Filed: November 11, 2009
    Publication date: November 10, 2011
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Akihiro Hachigo, Takao Nakamura, Masashi Yoshimura
  • Publication number: 20110223749
    Abstract: The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm?2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.
    Type: Application
    Filed: October 27, 2010
    Publication date: September 15, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiromu SHIOMI, Yu Saitoh, Kazuhide Sumiyoshi, Akihiro Hachigo, Makoto Kiyama, Seiji Nakahata
  • Patent number: 7960284
    Abstract: Affords a III-V compound semiconductor substrate manufacturing method that enables enhancement of the substrate PL intensity. In such a III-V compound semiconductor substrate manufacturing method, first, the surface 3a of a wafer 3 is polished (polishing step). Second, the surface 3a of the wafer 3 is cleaned (first cleaning step S7). Next, the surface 3a of the wafer 3 is subjected to first dry-etching, employing a halogen-containing gas, while first bias voltage is applied to a chuck 24 for carrying the wafer 3. Subsequently, the surface 3a of the wafer 3 is subjected to second dry-etching, employing the halogen-containing gas (second dry-etching step S11), while second bias power lower than the first bias power is applied to the chuck 24.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: June 14, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akihiro Hachigo, Naoki Matsumoto, Takayuki Nishiura
  • Publication number: 20110133207
    Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate (1) is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface (3) is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface (3) is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface (3) is not more than 3×1013, and a haze level of the surface (3) is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface (3) is not more than 2×1014, and a haze level of the surface (3) is not more than 5 ppm.
    Type: Application
    Filed: January 28, 2011
    Publication date: June 9, 2011
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Publication number: 20110133209
    Abstract: A GaN substrate on which an epitaxially grown layer of good quality can be formed is obtained. A GaN substrate as a group III nitride substrate has a surface in which the number of chlorine atoms per square centimeter of the surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013, wherein a plane orientation of the surface is any of a (0001) plane, a (11-20) plane, a (10-12) plane, a (10-10) plane, a (20-21) plane, a (10-11) plane, a (11-21) plane, a (11-22) plane, and a (11-24) plane of a wurtzite structure.
    Type: Application
    Filed: February 15, 2011
    Publication date: June 9, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji ISHIBASHI, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Publication number: 20110121311
    Abstract: The present invention provides a method for manufacturing a semiconductor substrate including a low-resistance nitride layer laminated on a substrate, a method for manufacturing a semiconductor device, a semiconductor substrate, and a semiconductor device. A method for manufacturing a semiconductor substrate of the present invention includes the following steps: A nitride substrate having a principal surface and a back surface opposite to the principal surface is prepared. Vapor-phase ions are implanted into the back surface of the nitride substrate. The back surface of the nitride substrate is bonded to a dissimilar substrate to form a bonded substrate. The nitride substrate is partially separated from the bonded substrate to form a laminated substrate including the dissimilar substrate and a nitride layer. The laminated substrate is heat-treated at a temperature over 700° C.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 26, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Fumitaka SATO, Akihiro HACHIGO, Naoki MATSUMOTO, Yoko MAEDA, Seiji NAKAHATA