Abstract: A control circuit generates a selection signal indicating a head area of an alignment buffer when the area is an unwritten area, and when the head area is a written area, successively performs comparison between a sequence number stored in the area and a sequence number of a target packet from a head to a tail to search a boundary area and generates a selection signal indicating the detected boundary area. When the boundary area could not be detected even when the search reaches the last written area, the control circuit generates a selection signal indicating the next area of the last written area. The writing circuit shifts data stored in each area by one area from the area indicated by the selection signal in a direction of the tail of the alignment buffer, and writes packet information of the target packet into the area indicated by the selection signal.

Abstract: A control circuit generates a selection signal indicating a head area of an alignment buffer when the area is an unwritten area, and when the head area is a written area, successively performs comparison between a sequence number stored in the area and a sequence number of a target packet from a head to a tail to search a boundary area and generates a selection signal indicating the detected boundary area. When the boundary area could not be detected even when the search reaches the last written area, the control circuit generates a selection signal indicating the next area of the last written area. The writing circuit shifts data stored in each area by one area from the area indicated by the selection signal in a direction of the tail of the alignment buffer, and writes packet information of the target packet into the area indicated by the selection signal.

Abstract: A control circuit generates a selection signal indicating a head area of an alignment buffer when the area is an unwritten area, and when the head area is a written area, successively performs comparison between a sequence number stored in the area and a sequence number of a target packet from a head to a tail to search a boundary area and generates a selection signal indicating the detected boundary area. When the boundary area could not be detected even when the search reaches the last written area, the control circuit generates a selection signal indicating the next area of the last written area. The writing circuit shifts data stored in each area by one area from the area indicated by the selection signal in a direction of the tail of the alignment buffer, and writes packet information of the target packet into the area indicated by the selection signal.

Abstract: Provided is an electrode manufacturing apparatus having a manufacturing unit mixing a plurality of materials and manufacturing an electrode slurry, a reservoir tank connected to the manufacturing unit and storing the manufactured electrode slurry that is manufactured, a coarse particle removal filter connected to the reservoir tank and removing coarse particles in a stored electrode slurry, a defoamer connected to the coarse particle removal filter and removing bubbles in the electrode slurry from which the coarse particles are removed and then returning the electrode slurry, from which the bubbles are removed, to a position below a liquid level of the electrode slurry stored in the reservoir tank, and a coating unit connected to the reservoir tank and coating the stored electrode slurry to a base material.

Abstract: A USB transmission control circuit of the present invention includes: a USB data control unit, which outputs transmission data to a USB bus; a USB transmission scheduler circuit, which designates the USB data control unit to perform transmission; FIFO memory, which stores data from an external memory; a FIFO controller, which controls the FIFO memory; a bus arbiter, which performs bus usage arbitration; a DMA controller; calculation means for calculating the difference between the amount of data written into FIFO memory by the FIFO controller and the amount of data sent out to the USB bus; and transmission means for commencing data transmission to the USB bus in conformity with an acknowledge signal from the bus arbiter, which authorizes bus usage, in response to a DMA request for writing data into FIFO memory.

Abstract: To implement a counter which can count clocks at high frequency exceeding the maximum operating frequency of the counter circuit, with a circuit with smaller circuit scale and lower power consumption, the present invention divides an externally set value HDB indicative of a count completion value into upper and lower bits, the upper bits being counted by using a counter circuit 12 with small circuit scale and power consumption, match being detected by a comparator 13. The clock signal is frequency divided to accommodate supply of high frequency clocks, and supplies it to the counter circuit 12. Then, the match detection signal of the upper bits is shifted in the number corresponding to the value of lower bits by a shift register 14 operating at a high frequency, and a count completion signal OUT is output.