Patents by Inventor Akihiro Usujima
Akihiro Usujima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9018067Abstract: A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth.Type: GrantFiled: December 20, 2013Date of Patent: April 28, 2015Assignee: Fujitsu Semiconductor LimitedInventor: Akihiro Usujima
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Patent number: 9012285Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.Type: GrantFiled: February 12, 2013Date of Patent: April 21, 2015Assignee: Fujitsu Semiconductor LimitedInventors: Akihiro Usujima, Shigeo Satoh
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Patent number: 8907430Abstract: A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film.Type: GrantFiled: November 9, 2009Date of Patent: December 9, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Akihiro Usujima, Junichi Ariyoshi, Taiji Ema
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Publication number: 20140252490Abstract: Disclosed is a semiconductor device including a semiconductor device including a substrate, a nitride semiconductor layer formed over the substrate and including an active region and an element isolation region, inert atoms being introduced into the element isolation region, a source electrode formed over the nitride semiconductor layer in the active region, a gate electrode formed over the nitride semiconductor layer in the active region away from the source electrode, and a drain electrode formed over the nitride semiconductor layer in the active region away from the gate electrode, the drain electrode including an end portion provided away from a boundary between the element isolation region and the active region by a first distance, wherein the first distance is greater than a second distance, the second distance being a distance where a concentration of the inert atoms diffused from the element isolation region into the active region becomes a first concentration, and an electron density in the active reType: ApplicationFiled: December 23, 2013Publication date: September 11, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Akihiro Usujima, Masamichi Kamiyama, Yasumori Miyazaki
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Patent number: 8790978Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.Type: GrantFiled: February 12, 2013Date of Patent: July 29, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Akihiro Usujima, Shigeo Satoh
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Publication number: 20140113422Abstract: A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth.Type: ApplicationFiled: December 20, 2013Publication date: April 24, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Akihiro Usujima
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Patent number: 8683406Abstract: A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.Type: GrantFiled: August 6, 2012Date of Patent: March 25, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Mitsuaki Igeta, Masahiro Sueda, Rikio Takase, Akihiro Usujima
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Patent number: 8637938Abstract: A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth.Type: GrantFiled: December 2, 2010Date of Patent: January 28, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Akihiro Usujima
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Patent number: 8552506Abstract: A method of manufacturing a semiconductor device includes forming a first and a second isolation insulating film to define a first, a second, a third and a fourth region, forming a first insulating film, implanting a first impurity of a first conductivity type through the first insulating film into the first, the second and the fourth region at a first depth, forming a second insulating film thinner than the first insulating film, implanting a second impurity of a second conductivity type through the second insulating film into the third region at a second depth in the semiconductor substrate, implanting a third impurity of the second conductivity type into the third region at a third depth shallower than the second depth, forming a first transistor of the first conductivity type in the third region, and forming a second transistor of the second conductivity type in the fourth region.Type: GrantFiled: June 8, 2012Date of Patent: October 8, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Akihiro Usujima, Shigeo Satoh
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Patent number: 8470656Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.Type: GrantFiled: July 9, 2012Date of Patent: June 25, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Akihiro Usujima, Shigeo Satoh
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Publication number: 20120297353Abstract: A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.Type: ApplicationFiled: August 6, 2012Publication date: November 22, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Mitsuaki IGETA, Masahiro SUEDA, Rikio TAKASE, Akihiro USUJIMA
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Publication number: 20120273853Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.Type: ApplicationFiled: July 9, 2012Publication date: November 1, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Akihiro USUJIMA, Shigeo SATOH
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Publication number: 20120276710Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.Type: ApplicationFiled: July 9, 2012Publication date: November 1, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Akihiro USUJIMA, Shigeo Satoh
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Publication number: 20120273896Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.Type: ApplicationFiled: July 9, 2012Publication date: November 1, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Akihiro USUJIMA, Shigeo SATOH
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Publication number: 20120241869Abstract: A method of manufacturing a semiconductor device includes forming a first and a second isolation insulating film to define a first, a second, a third and a fourth region, forming a first insulating film, implanting a first impurity of a first conductivity type through the first insulating film into the first, the second and the fourth region at a first depth, forming a second insulating film thinner than the first insulating film, implanting a second impurity of a second conductivity type through the second insulating film into the third region at a second depth in the semiconductor substrate, implanting a third impurity of the second conductivity type into the third region at a third depth shallower than the second depth, forming a first transistor of the first conductivity type in the third region, and forming a second transistor of the second conductivity type in the fourth region.Type: ApplicationFiled: June 8, 2012Publication date: September 27, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Akihiro USUJIMA, Shigeo SATOH
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Patent number: 8237219Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.Type: GrantFiled: September 8, 2010Date of Patent: August 7, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Akihiro Usujima, Shigeo Satoh
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Patent number: 8216895Abstract: A method of manufacturing a semiconductor device includes forming a first and a second isolation insulating film to define a first, a second, a third and a fourth region, forming a first insulating film, implanting a first impurity of a first conductivity type through the first insulating film into the first, the second and the fourth region at a first depth, forming a second insulating film thinner than the first insulating film, implanting a second impurity of a second conductivity type through the second insulating film into the third region at a second depth in the semiconductor substrate, implanting a third impurity of the second conductivity type into the third region at a third depth shallower than the second depth, forming a first transistor of the first conductivity type in the third region, and forming a second transistor of the second conductivity type in the fourth region.Type: GrantFiled: July 9, 2010Date of Patent: July 10, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Akihiro Usujima, Shigeo Satoh
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Publication number: 20110156173Abstract: A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth.Type: ApplicationFiled: December 2, 2010Publication date: June 30, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Akihiro Usujima
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Patent number: 7906819Abstract: The semiconductor device includes the concentration of the impurity of the first conductivity type in a doped channel layer of a first conductivity type in the pass transistor is set at a relatively low value, and pocket regions of the first conductivity type in a pass transistor are formed so as to be relatively shallow with a relatively high impurity concentration.Type: GrantFiled: January 8, 2009Date of Patent: March 15, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Akihiro Usujima, Hideyuki Kojima
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Publication number: 20110057253Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.Type: ApplicationFiled: September 8, 2010Publication date: March 10, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Akihiro USUJIMA, Shigeo SATOH