Patents by Inventor Akihisa Fujimoto
Akihisa Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11573701Abstract: According to one embodiment, a memory device includes a nonvolatile semiconductor memory having physical storage areas that includes a user area externally accessible and are divided into management units and a control unit. The control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns a management unit represented by an address of the read command or the write command as the sequential write area, and changes memory access control by judging whether an address of a memory access command to access the user area indicates access in the sequential write area whose size is equivalent to the management unit.Type: GrantFiled: March 9, 2021Date of Patent: February 7, 2023Assignee: KIOXIA CORPORATIONInventor: Akihisa Fujimoto
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Publication number: 20220382318Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.Type: ApplicationFiled: August 11, 2022Publication date: December 1, 2022Applicant: Kioxia CorporationInventors: Toshitada SAITO, Akihisa FUJIMOTO
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Patent number: 11460878Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.Type: GrantFiled: July 14, 2021Date of Patent: October 4, 2022Assignee: Kioxia CorporationInventors: Toshitada Saito, Akihisa Fujimoto
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Publication number: 20220026980Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Applicant: Kioxia CorporationInventor: Akihisa FUJIMOTO
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Publication number: 20220005520Abstract: A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.Type: ApplicationFiled: September 22, 2021Publication date: January 6, 2022Applicant: KIOXIA CORPORATIONInventor: Akihisa FUJIMOTO
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Patent number: 11169594Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.Type: GrantFiled: June 30, 2020Date of Patent: November 9, 2021Assignee: Kioxia CorporationInventor: Akihisa Fujimoto
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Publication number: 20210341961Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.Type: ApplicationFiled: July 14, 2021Publication date: November 4, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Toshitada SAITO, Akihisa FUJIMOTO
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Publication number: 20210334617Abstract: According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.Type: ApplicationFiled: July 7, 2021Publication date: October 28, 2021Applicant: Kioxia CorporationInventors: Akihisa FUJIMOTO, Toshitada SAITO, Noriya SAKAMOTO, Atsushi KONDO
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Patent number: 11158365Abstract: A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.Type: GrantFiled: June 26, 2020Date of Patent: October 26, 2021Assignee: Kioxia CorporationInventor: Akihisa Fujimoto
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Publication number: 20210312971Abstract: According to one embodiment, an information processing apparatus includes a connector into which a first-type semiconductor storage device operating with n types of power supply voltages or a second-type semiconductor storage device operating with m types of power supply voltages less than the n types of power supply voltages is capable of being placed. The apparatus checks whether or not a notch is formed at a predetermined position of a semiconductor storage device placed into the connector, and supplies the m types of power supply voltages to the semiconductor storage device when the notch is formed at the predetermined position.Type: ApplicationFiled: June 15, 2021Publication date: October 7, 2021Applicant: Kioxia CorporationInventors: Akihisa FUJIMOTO, Atsushi KONDO
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Patent number: 11099597Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.Type: GrantFiled: April 19, 2019Date of Patent: August 24, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Toshitada Saito, Akihisa Fujimoto
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Patent number: 11093811Abstract: A memory card includes a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, wherein N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, wherein K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.Type: GrantFiled: March 9, 2018Date of Patent: August 17, 2021Assignee: Kioxia CorporationInventors: Akihisa Fujimoto, Toshitada Saito, Noriya Sakamoto, Atsushi Kondo
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Patent number: 11081163Abstract: According to one embodiment, an information processing apparatus includes a connector into which a first-type semiconductor storage device operating with n types of power supply voltages or a second-type semiconductor storage device operating with m types of power supply voltages less than the n types of power supply voltages is capable of being placed. The apparatus checks whether or not a notch is formed at a predetermined position of a semiconductor storage device placed into the connector, and supplies the m types of power supply voltages to the semiconductor storage device when the notch is formed at the predetermined position.Type: GrantFiled: March 13, 2020Date of Patent: August 3, 2021Assignee: Kioxia CorporationInventors: Akihisa Fujimoto, Atsushi Kondo
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Publication number: 20210191621Abstract: According to one embodiment, a memory device includes a nonvolatile semiconductor memory having physical storage areas that includes a user area externally accessible and are divided into management units and a control unit. The control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns a management unit represented by an address of the read command or the write command as the sequential write area, and changes memory access control by judging whether an address of a memory access command to access the user area indicates access in the sequential write area whose size is equivalent to the management unit.Type: ApplicationFiled: March 9, 2021Publication date: June 24, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventor: Akihisa FUJIMOTO
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Patent number: RE48514Abstract: According to one embodiment, a semiconductor device includes a device. The device includes a decoder, a generation circuit, a register, and a modifier. The decoder analyzes a command of a received packet. The generation circuit generates a unique device number in accordance with information in the packet. The register holds the generated unique device number. The modifier updates and outputs the packet. When a packet issued by a host is a command packet, among broadcast packets which return to the host through one or more devices, for determining the unique device number, the command packet includes parameters of an initial value and final value of device number.Type: GrantFiled: December 28, 2018Date of Patent: April 13, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Akihisa Fujimoto
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Patent number: RE48736Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.Type: GrantFiled: September 3, 2019Date of Patent: September 14, 2021Assignee: Kioxia CorporationInventor: Akihisa Fujimoto
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Patent number: RE48772Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.Type: GrantFiled: June 24, 2019Date of Patent: October 12, 2021Assignee: KIOXIA CORPORATIONInventor: Akihisa Fujimoto
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Patent number: RE48983Abstract: A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.Type: GrantFiled: March 20, 2017Date of Patent: March 22, 2022Assignee: TOSHIBA MEMORY CORPORATIONInventor: Akihisa Fujimoto
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Patent number: RE48997Abstract: According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device, a control section, a memory, an extended function section, and an extension register. The extended function section is controlled by the control section. A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.Type: GrantFiled: June 25, 2019Date of Patent: March 29, 2022Assignee: KIOXIA CORPORATIONInventors: Akihisa Fujimoto, Hiroyuki Sakamoto
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Patent number: RE49235Abstract: A memory card 100 having a NAND type flash memory connectable to a host device 200, capable of transmitting/receiving a signal to/from the host device 200 at a first voltage (3.3 V) or a second voltage (1.8 V) and safely changing a signal voltage of a transmission/reception signal that mutually checks a signal voltage through handshake processing with the host device 200 when the signal voltage is switched.Type: GrantFiled: December 28, 2020Date of Patent: October 4, 2022Assignee: Kioxia CorporationInventor: Akihisa Fujimoto