Patents by Inventor Akihisa Koyama

Akihisa Koyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230394088
    Abstract: Provided is an information sharing system including at least one processor configured to: acquire a use status of use by each of a plurality of users for each of a plurality of functions relating to an information sharing service for sharing information; and execute, for each of the functions, predetermined processing relating to the function based on the use status of the function.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 7, 2023
    Inventors: Akihisa KOYAMA, Ryotaro NAKAGAWA, Shuyo NAKATANI
  • Patent number: 6765510
    Abstract: An EBCOT codec (1) is provided which includes a bit modeling unit (11), arithmetic codec (12), input FIFO memory (13), output FIFO memory (14) and a controller (16). The input and output FIFO memories (13) and (14) have a function to control the bit length of to-be-stored data correspondingly to that of supplied data. For the coding, the input FIFO memory (13) is supplied with a wavelet transform coefficient of 16 bits, and for the decoding, it is supplied with a code data of 8 bits. For the coding, the output FIFO memory (14) outputs 8-bit code data, and for the decoding, it outputs wavelet transform coefficients of 16 bits. Thus, the circuit scale can be reduced and data transfer speed be improved.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: July 20, 2004
    Assignee: Sony Corporation
    Inventors: Akihisa Koyama, Yasushi Nishi
  • Publication number: 20030156050
    Abstract: An EBCOT codec (1) is provided which includes a bit modeling unit (11), arithmetic codec (12), input FIFO memory (13), output FIFO memory (14) and a controller (16). The input and output FIFO memories (13) and (14) have a function to control the bit length of to-be-stored data correspondingly to that of supplied data. For the coding, the input FIFO memory (13) is supplied with a wavelet transform coefficient of 16 bits, and for the decoding, it is supplied with a code data of 8 bits. For the coding, the output FIFO memory (14) outputs 8-bit code data, and for the decoding, it outputs wavelet transform coefficients of 16 bits. Thus, the circuit scale can be reduced and data transfer speed be improved.
    Type: Application
    Filed: February 20, 2003
    Publication date: August 21, 2003
    Inventors: Akihisa Koyama, Yasushi Nishi
  • Patent number: 5368665
    Abstract: A method of applying porous building plates includes applying plate-like porous building plates having pores on the surfaces and then jointing them by means of a coated joint method. In the method, the pores on the surfaces of the porous building plates are packed with an acid soluble substance and then the plates are joined by means of a coated joint method. Subsequently, the surfaces of the porous building plates are washed with an acid.
    Type: Grant
    Filed: December 1, 1992
    Date of Patent: November 29, 1994
    Assignee: INAX Corporation
    Inventors: Akihisa Koyama, Syoji Kitahara, Tomonori Honda