Patents by Inventor Akihisa Nakahashi

Akihisa Nakahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230070635
    Abstract: Experimental device machining is performed according to plan information including first type information indicating a first type condition of the experimental device machining and second type information indicating a second type condition of the experimental device machining. Third type information indicating a third type result and fourth type information indicating a fourth type result are acquired. Extended plan information is acquired in which a uniformity of extended second type information and extended third type information is equal to or greater than a threshold value. Extended third type information indicating a third type result and extended fourth type information indicating a fourth type result are acquired by performing the experimental device machining according to the extended plan information. An extended first relationship is derived that is a relationship between extended first type information, the extended second type information, and the extended third type information.
    Type: Application
    Filed: August 26, 2022
    Publication date: March 9, 2023
    Inventors: NOBUO HARA, HIROKO YOSHIDA, AKIHISA NAKAHASHI
  • Publication number: 20220067015
    Abstract: An information processing method includes: creating a first table; calculating a first response surface using the first table in which an object variable is recorded, the object variable acquired when experimental conditions of a first control factor is fixed to a first level value; adding the experimental conditions of the first control factor in which the first level value is set to the first table when the first response surface does not include a target value related to the object variable; creating a second table by adding a plurality of combinations of the experimental conditions for each of the plurality of control factors in which a first plurality of level values are set and the first control factor in which a second plurality of level values are set to the first table; calculating a second response surface including the target value using the second table; and outputting the second response surface.
    Type: Application
    Filed: August 6, 2021
    Publication date: March 3, 2022
    Inventors: NOBUO HARA, MIKIO USHIODA, AKIHISA NAKAHASHI
  • Publication number: 20220067237
    Abstract: An information processing method includes: creating a first table by an experimental design method, calculating a first response surface using the first table, setting a fourth level value for a first control factor when the first response surface does not include a target value related to an object variable for the first control factor, creating a second table by the experimental design method by deleting at least one combination of the experimental conditions which include one level value for the first control factor from the first table and adding at least one combination of the experimental conditions based on the plurality of level values including the fourth level value and without including the one level value for the first control factor, calculating a second response surface including the target value using the second table, and outputting the second response surface.
    Type: Application
    Filed: August 6, 2021
    Publication date: March 3, 2022
    Inventors: Nobuo HARA, Mikio USHIODA, Akihisa NAKAHASHI
  • Publication number: 20210390227
    Abstract: An experiment of processing a device is performed to acquire type 1 information and type 2 information indicating processing conditions, and type 3 information and type 4 information indicating results of the processing, derive a first relation between the type 1 information, the type 2 information, and the type 3 information, and a second relation between the type 1 information, the type 2 information, and the type 4 information, and generate and output a model that estimates the type 4 information indicating a result of the processing by using the first relation and the second relation with the type 2 information and the type 3 information that are measured during the processing as inputs.
    Type: Application
    Filed: May 18, 2021
    Publication date: December 16, 2021
    Inventors: HIROKO YOSHIDA, NOBUO HARA, KOICHI WAKITANI, AKIHISA NAKAHASHI
  • Patent number: 9741885
    Abstract: A plurality of solar cells are arranged in a first direction and each provided with first and second electrodes on a one main surface side thereof. A wiring member includes a conductive layer and a resin sheet supporting the conductive layer, the conductive layer electrically connecting the first electrode of one of the solar cells adjacent to each other in the first direction to the second electrode of another one of the solar cells. An adhesive layer bonds the wiring member to each of the solar cells. The wiring member includes a first bonded portion bonded to the one solar cell via the adhesive layer, a second bonded portion bonded to the other solar cell via the adhesive layer, and a connection portion connecting the first bonded portion and the second bonded portion together, and an opening is provided in the conductive layer in the connection portion.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: August 22, 2017
    Assignee: Panasonic Intellectual Property Management Co. Ltd.
    Inventors: Yousuke Ishii, Yoshiyuki Kudoh, Akihisa Nakahashi
  • Publication number: 20160226436
    Abstract: A long-side frame piece has a cylindrical portion. The cylindrical portion is formed from one side end along the direction in which the long-side frame piece extends to the other side end. The cylindrical portion has threaded holes. The threaded holes are provided inside a through hole. Screws are inserted in the threaded holes. A short-side frame piece has a plate-shaped portion. The plate-shaped portion covers the end of the cylindrical portion in the direction in which the long-side frame piece extends Openings are formed in the plate-shaped portion, through which pass the screws inserted in the threaded holes. The plate-shaped portion has a cutout exposing a portion of the module body from a first surface toward a second surface, formed closer to a first direction side than the threaded holes of the through hole.
    Type: Application
    Filed: April 7, 2016
    Publication date: August 4, 2016
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yuki OKUDA, Akihisa NAKAHASHI
  • Patent number: 9337770
    Abstract: A long-side frame piece has a cylindrical portion. The cylindrical portion is formed from one side end along the direction in which the long-side frame piece extends to the other side end. The cylindrical portion has threaded holes. The threaded holes are provided inside a through hole. Screws are inserted in the threaded holes. A short-side frame piece has a plate-shaped portion. The plate-shaped portion covers the end of the cylindrical portion in the direction in which the long-side frame piece extends. Openings are formed in the plate-shaped portion, through which pass the screws inserted in the threaded holes. The plate-shaped portion has a cutout exposing a portion of the module body from a first surface toward a second surface, formed closer to a first direction side than the threaded holes of the through hole.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: May 10, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yuki Okuda, Akihisa Nakahashi
  • Publication number: 20150188485
    Abstract: A long-side frame piece has a cylindrical portion. The cylindrical portion is formed from one side end along the direction in which the long-side frame piece extends to the other side end. The cylindrical portion has threaded holes. The threaded holes are provided inside a through hole. Screws are inserted in the threaded holes. A short-side frame piece has a plate-shaped portion. The plate-shaped portion covers the end of the cylindrical portion in the direction in which the long-side frame piece extends. Openings are formed in the plate-shaped portion, through which pass the screws inserted in the threaded holes. The plate-shaped portion has a cutout exposing a portion of the module body from a first surface toward a second surface, formed closer to a first direction side than the threaded holes of the through hole.
    Type: Application
    Filed: March 13, 2015
    Publication date: July 2, 2015
    Inventors: Yuki OKUDA, Akihisa NAKAHASHI
  • Publication number: 20150040961
    Abstract: A plurality of solar cells are arranged in a first direction and each provided with first and second electrodes on a one main surface side thereof. A wiring member includes a conductive layer and a resin sheet supporting the conductive layer, the conductive layer electrically connecting the first electrode of one of the solar cells adjacent to each other in the first direction to the second electrode of another one of the solar cells. An adhesive layer bonds the wiring member to each of the solar cells. The wiring member includes a first bonded portion bonded to the one solar cell via the adhesive layer, a second bonded portion bonded to the other solar cell via the adhesive layer, and a connection portion connecting the first bonded portion and the second bonded portion together, and an opening is provided in the conductive layer in the connection portion.
    Type: Application
    Filed: October 23, 2014
    Publication date: February 12, 2015
    Inventors: Yousuke ISHII, Yoshiyuki KUDOH, Akihisa NAKAHASHI
  • Patent number: 8772052
    Abstract: Disclosed is a method for manufacturing an organic EL display, which comprises: a step of preparing an organic EL panel that comprises a substrate and organic EL elements arranged as a matrix on the substrate, wherein each organic EL element has a pixel electrode arranged on the substrate, an organic layer arranged on the pixel electrode, a transparent counter electrode arranged on the organic layer, a protective layer arranged on the transparent counter electrode, and a color filter arranged on the protective layer, and a defect portion present in the organic layer in each organic EL element is detected; a step of destroying a region of the transparent counter electrode positioned above the defect portion by irradiating the region with laser light through the color filter; and a step wherein a region of the color filter positioned above the defect portion is removed.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: July 8, 2014
    Assignee: Panasonic Corporation
    Inventors: Kazutoshi Miyazawa, Akihisa Nakahashi
  • Patent number: 8337267
    Abstract: There are provided an organic electro-luminescence device with filters and a method for repairing the same which are capable of reducing variations in conditions for leak-light transmission during leak-light detection and conditions for transmission of laser light used for repairing, depending on respective types of filters.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: December 25, 2012
    Assignee: Panasonic Corporation
    Inventors: Noriyuki Suzuki, Shinsuke Komatsu, Akihisa Nakahashi
  • Patent number: 8283661
    Abstract: Provided is an organic EL display manufacturing method which has: a step wherein an organic EL panel having a substrate and organic EL elements arranged in matrix on the substrate is prepared, and each organic EL element is permitted to have a pixel electrode disposed on the substrate, an organic layer disposed on the pixel electrode, a transparent counter electrode disposed on the organic layer, a sealing layer disposed on the transparent counter electrode, and a color filter disposed on the sealing layer; a step of detecting a defective portion on the organic layer in the organic EL element; and a step of breaking the transparent counter electrode in a region on the defective portion of the transparent counter electrode by irradiating the region on the defective portion with a laser beam. The laser beam is radiated by being tilted with respect to the normal line on the display surface of the organic EL panel.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: October 9, 2012
    Assignee: Panasonic Corporation
    Inventors: Kazutoshi Miyazawa, Akihisa Nakahashi
  • Patent number: 8093505
    Abstract: Provided is a layered electronic circuit device capable of realizing high-density/high-function mounting, easily inspecting and repairing the respective constituent elements, and improving the electronic connection characteristic. The layered electronic circuit device includes a first circuit substrate (101) and a second circuit substrate (102) which are arranged in parallel such that their substrate surfaces are opposed to each other. The peripheral portion of the first circuit substrate (101) and the peripheral portion of the second circuit substrate (102) are connected to each other by connection members (10a to 10d) having a wiring member (103) and a thermal hardening anisotropic conductive sheet (107), thereby performing electric connection.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: January 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Manabu Gokan, Akihisa Nakahashi, Takayuki Hirose, Yoko Kasai, Kohichi Tanda
  • Publication number: 20110278603
    Abstract: Disclosed is a method for manufacturing an organic EL display, which comprises: a step of preparing an organic EL panel that comprises a substrate and organic EL elements arranged as a matrix on the substrate, wherein each organic EL element has a pixel electrode arranged on the substrate, an organic layer arranged on the pixel electrode, a transparent counter electrode arranged on the organic layer, a protective layer arranged on the transparent counter electrode, and a color filter arranged on the protective layer, and a defect portion present in the organic layer in each organic EL element is detected; a step of destroying a region of the transparent counter electrode positioned above the defect portion by irradiating the region with laser light through the color filter; and a step wherein a region of the color filter positioned above the defect portion is removed.
    Type: Application
    Filed: January 21, 2010
    Publication date: November 17, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Kazutoshi Miyazawa, Akihisa Nakahashi
  • Publication number: 20110227104
    Abstract: Provided is an organic EL display manufacturing method which has: a step wherein an organic EL panel having a substrate and organic EL elements arranged in matrix on the substrate is prepared, and each organic EL element is permitted to have a pixel electrode disposed on the substrate, an organic layer disposed on the pixel electrode, a transparent counter electrode disposed on the organic layer, a sealing layer disposed on the transparent counter electrode, and a color filter disposed on the sealing layer; a step of detecting a defective portion on the organic layer in the organic EL element; and a step of breaking the transparent counter electrode in a region on the defective portion of the transparent counter electrode by irradiating the region on the defective portion with a laser beam. The laser beam is radiated by being tilted with respect to the normal line on the display surface of the organic EL panel.
    Type: Application
    Filed: April 20, 2010
    Publication date: September 22, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Kazutoshi Miyazawa, Akihisa Nakahashi
  • Publication number: 20110037377
    Abstract: There are provided an organic electro-luminescence device with filters and a method for repairing the same which are capable of reducing variations in conditions for leak-light transmission during leak-light detection and conditions for transmission of laser light used for repairing, depending on respective types of filters.
    Type: Application
    Filed: November 25, 2009
    Publication date: February 17, 2011
    Inventors: Noriyuki Suzuki, Shinsuke Komatsu, Akihisa Nakahashi
  • Patent number: 7875974
    Abstract: To provide a stacked mounting structure in which the number of semiconductor chips that can be stacked is greater than conventionally, as well as a method for fabricating the same, each semiconductor chip has electrodes provided at least at one end in the stacked mounting structure, and a board holding the semiconductor chips at the one end is folded with at least two of the semiconductor chips being stacked so as to at least partially overlap with each other.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: January 25, 2011
    Assignee: Panasonic Corporation
    Inventors: Manabu Gokan, Akihisa Nakahashi, Naoki Suzuki, Haneo Iwamoto, Satoru Yuhaku
  • Patent number: 7808094
    Abstract: A stacked structure of semiconductor chips includes plural stacked semiconductor chips and plural tabular holding members which hold the respective semiconductor chips.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: October 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Manabu Gokan, Akihisa Nakahashi, Koichi Nagai, Naoki Suzuki
  • Publication number: 20100230147
    Abstract: Provided is a layered electronic circuit device capable of realizing high-density/high-function mounting, easily inspecting and repairing the respective constituent elements, and improving the electronic connection characteristic. The layered electronic circuit device includes a first circuit substrate (101) and a second circuit substrate (102) which are arranged in parallel such that their substrate surfaces are opposed to each other. The peripheral portion of the first circuit substrate (101) and the peripheral portion of the second circuit substrate (102) are connected to each other by connection members (10a to 10d) having a wiring member (103) and a thermal hardening anisotropic conductive sheet (107), thereby performing electric connection.
    Type: Application
    Filed: August 10, 2007
    Publication date: September 16, 2010
    Applicant: Panasonic Corporation
    Inventors: Manabu Gokan, Akihisa Nakahashi, Takayuki Hirose, Yoko Kasai, Kohichi Tanda
  • Patent number: 7638888
    Abstract: There is provided a semiconductor chip mounting substrate including a substrate on which a mounting region for mounting a semiconductor chip and a connection region for interlayer connection of the semiconductor chip are formed, and a plurality of alignment marks for alignment at the time of stacking which are provided around or in the connection region on the substrate, wherein a reinforcing member as a reinforcing region for reinforcing a portion between the plurality of alignment marks is provided on the substrate.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: December 29, 2009
    Assignee: Panasonic Corporation
    Inventors: Naoki Suzuki, Akihisa Nakahashi, Yukihiro Maegawa