Abstract: A method of making a semiconductor structure includes forming an alternating stack of insulating layers and sacrificial material layers, forming initial vertical stacks of at least one initial insulating plate and at least one initial dielectric material plate, and performing a plurality of pattern transfer process sequences that transfers the pattern of the initial vertical stacks by different numbers of underlying layers to form final vertical stacks of at least one final insulating plate and at least one final dielectric material plate. Sacrificial material layers that underlie the final vertical stacks are replaced with electrically conductive layers. The final dielectric material plates or conductive material plates formed by replacement of the dielectric material plates are employed as etch stop structures during subsequent formation of layer contact via structures.

Abstract: A memory device includes alternating stacks of insulating layers and electrically conductive layers that are laterally spaced apart from each other along a second horizontal direction, laterally extend along the first horizontal direction through an inter-array region, a first memory array region and a second memory array region that is laterally spaced apart along the first horizontal direction from the memory array region by the inter-array region. Each electrically conductive layer within the alternating stacks has a respective bridge region having a respective strip width along the second horizontal direction within the inter-array region, and the strip width of a topmost electrically conductive layer in a first-tier alternating stack is smaller than the strip width of a topmost electrically conductive layer in a second-tier alternating stack which overlies the first-tier alternating stack.

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. Bridge structures are formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the bridge structure are present within the backside trenches.

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. A set of one or more bridge structures including a doped semiconductor material is formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the sets of at least one bridge structure are present within the backside trenches.

Abstract: An alternating stack of insulating layers and word-line-level spacer material layers is formed over a substrate. Memory opening fill structures including a respective memory film, a respective word-line-level semiconductor channel portion, a respective word-line-level dielectric core laterally, and a respective sacrificial dielectric material portion are formed through the alternating stack. Drain-select-level material layers are formed over the alternating stack and the memory opening fill structures. Drain-select-level openings are formed through the drain-select-level material layers and over the memory opening fill structures. The sacrificial dielectric material portions are removed selective to the word-line-level semiconductor channel portions underneath the drain-select-level openings. Drain-select-level semiconductor channel portions are formed directly on a respective one of the word-line-level semiconductor channel portions.

Abstract: Memory openings and support openings are formed in a memory array region and a staircase region, respectively, through an alternating stack of insulating layers and spacer material layers. Pedestal channel portions and pedestal semiconductor portions are formed at the bottom of the memory openings and the support openings, respectively. Semiconductor oxide plates are provided only in a distal subset of the support openings that are spaced from the memory array region by more than a threshold separation distance. Memory openings are filled with memory opening fill structures, and support openings are filled with support pillar structures. Proximal support pillar structures located adjacent to the memory array region provide internal electrically conductive paths for discharging accumulated electrical charges.

Abstract: An alternating stack of insulating layers and word-line-level spacer material layers is formed over a substrate. Memory opening fill structures including a respective memory film, a respective word-line-level semiconductor channel portion, a respective word-line-level dielectric core laterally, and a respective sacrificial dielectric material portion are formed through the alternating stack. Drain-select-level material layers are formed over the alternating stack and the memory opening fill structures. Drain-select-level openings are formed through the drain-select-level material layers and over the memory opening fill structures. The sacrificial dielectric material portions are removed selective to the word-line-level semiconductor channel portions underneath the drain-select-level openings. Drain-select-level semiconductor channel portions are formed directly on a respective one of the word-line-level semiconductor channel portions.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are replaced with, electrically conductive layers. An insulating cap layer is formed over the alternating stack. After formation of memory stack structures through each layer of the alternating stack and the insulating cap layer, a line trench straddling a neighboring pair of rows of the memory stack is formed. Sidewalls of the line trench include a sidewall of each memory stack structure within the neighboring pair of rows of the memory stack structures. A drain select gate dielectric and a drain select electrode line are formed within the line trench. The drain select electrode line controls flow of electrical current through an upper portion of a vertical semiconductor channel within each memory stack structure below the drain regions to activate or deactivate the neighboring rows.

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are replaced with, electrically conductive layers. An insulating cap layer is formed over the alternating stack. After formation of memory stack structures through each layer of the alternating stack and the insulating cap layer, a line trench straddling a neighboring pair of rows of the memory stack is formed. Sidewalls of the line trench include a sidewall of each memory stack structure within the neighboring pair of rows of the memory stack structures. A drain select gate dielectric and a drain select electrode line are formed within the line trench. The drain select electrode line controls flow of electrical current through an upper portion of a vertical semiconductor channel within each memory stack structure below the drain regions to activate or deactivate the neighboring rows.

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.