Patents by Inventor Akihisa Yamaguchi
Akihisa Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11926432Abstract: This fuel tank dam closes a gap between a first structural component fixed to the inside surface of the outer plate of a fuel tank and a second structural component provided with a cutout part into which the first structural component is inserted. This fuel tank dam includes: a first portion that can be fixed to the first structural component; a second portion that has a surface extending in a direction intersecting with the first portion and can be fixed to the second structural component; and a third portion that has a bellows and is disposed between the first portion and the second portion. This fuel tank dam is configured such that the first portion, the second portion, and the third portion are integrated, the bellows has a thickness of 0.381 to 1.524 mm, and the second portion has a thickness of 0.762 to 7.620 mm.Type: GrantFiled: May 21, 2019Date of Patent: March 12, 2024Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Eizaburo Yamaguchi, Tadasuke Kurita, Hajime Tada, Akihiko Hirota, Akihisa Okuda, Kana Sakon
-
Patent number: 10852222Abstract: A method of inspecting a degree of air bubbles which are mixed into an ultraviolet curable resin for an optical fiber having viscosity of 1.2 Pa·s to 6.2 Pa·s at a temperature of 25±5° C., is performed in such a manner that the ultraviolet curable resin for an optical fiber which is an inspecting target is put into a sealed apparatus, then the inside of the sealed apparatus is decompressed to be a predetermined pressure, and then the sealed apparatus is left to stand as it is for a predetermined time. If a ratio of the volume expansion of the ultraviolet curable resin for an optical fiber is equal to or less than a predetermined threshold, the ultraviolet curable resin for an optical fiber is recognized as an accepted product.Type: GrantFiled: March 23, 2016Date of Patent: December 1, 2020Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Akihisa Yamaguchi, Masayuki Kato, Hitoshi Tsubakiyama
-
Publication number: 20160282250Abstract: A method of inspecting a degree of air bubbles which are mixed into an ultraviolet curable resin for an optical fiber having viscosity of 1.2 Pa·s to 6.2 Pa·s at a temperature of 25±5° C., is performed in such a manner that the ultraviolet curable resin for an optical fiber which is an inspecting target is put into a sealed apparatus, then the inside of the sealed apparatus is decompressed to be a predetermined pressure, and then the sealed apparatus is left to stand as it is for a predetermined time. If a ratio of the volume expansion of the ultraviolet curable resin for an optical fiber is equal to or less than a predetermined threshold, the ultraviolet curable resin for an optical fiber is recognized as an accepted product.Type: ApplicationFiled: March 23, 2016Publication date: September 29, 2016Inventors: Akihisa YAMAGUCHI, Masayuki KATO, Hitoshi TSUBAKIYAMA
-
Patent number: 9018076Abstract: A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region.Type: GrantFiled: January 21, 2013Date of Patent: April 28, 2015Assignee: Fujitsu Semiconductor LimitedInventors: Hiroyuki Ogawa, Akihisa Yamaguchi
-
Patent number: 8907429Abstract: A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well.Type: GrantFiled: February 15, 2013Date of Patent: December 9, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Eiji Yoshida, Akihisa Yamaguchi
-
Patent number: 8675383Abstract: Memory cells adjacent to each other in a second direction are formed in a first p-type well region, a first n-type well region, and a second p-type well region arranged in a first direction. Each memory cell includes a first transfer transistor and a first driver transistor formed in the first p-type well region, a second transfer transistor and a second driver transistor formed in the second p-type well region, and first and second load transistors formed in the first n-type well region. In an SRAM, gate electrodes of the first and second transfer transistors of the memory cells adjacent to each other in the second direction are electrically connected to first and second word lines, respectively. The first and second word lines are electrically connected to the first and second p-type well regions, respectively.Type: GrantFiled: October 3, 2012Date of Patent: March 18, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Akihisa Yamaguchi, Eiji Yoshida
-
Patent number: 8399932Abstract: A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well.Type: GrantFiled: May 31, 2011Date of Patent: March 19, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Eiji Yoshida, Akihisa Yamaguchi
-
Patent number: 8379428Abstract: A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region.Type: GrantFiled: October 28, 2010Date of Patent: February 19, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Hiroyuki Ogawa, Akihisa Yamaguchi
-
Publication number: 20120032272Abstract: A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well.Type: ApplicationFiled: May 31, 2011Publication date: February 9, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Eiji Yoshida, Akihisa Yamaguchi
-
Publication number: 20110101434Abstract: A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region.Type: ApplicationFiled: October 28, 2010Publication date: May 5, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hiroyuki OGAWA, Akihisa YAMAGUCHI
-
Patent number: 6960502Abstract: A reduction of a leakage current as well as a decrease in the thickness of an insulating film is realized in a semiconductor device. To this end, a silicon oxide film and a silicon nitride film are formed on a substrate, which is then heated to a temperature within a range of 20° C.–600° C. so that a plasma nitridation process can be performed on the silicon nitride film. Further, a thermal process is performed in a non-oxide gas atmosphere. By performing these processes, the gate leakage current can be significantly reduced in the formed gate insulator, and the silicon oxide-equivalent thickness of the insulating film can be significantly decreased as well.Type: GrantFiled: January 27, 2003Date of Patent: November 1, 2005Assignee: Fujitsu LimitedInventor: Akihisa Yamaguchi
-
Publication number: 20050220309Abstract: In a recording unit, a set state table in which various parameters which are required are stored when a sound processing unit performs signal processing for audio data that corresponds to each channel, and a setting screen data are recorded. This setting screen data is linked to the set state table, so that the set state table is altered in accordance with alteration performed on this setting screen. As a result, the parameters that are used when the sound processing unit performs signal processing for audio data are altered.Type: ApplicationFiled: March 24, 2005Publication date: October 6, 2005Inventors: Mikiko Hirata, Akihisa Yamaguchi, Junichi Imamura, Jun Peng, Susumu Yamamoto
-
Publication number: 20030232491Abstract: A reduction of a leakage current as well as a decrease in the thickness of an insulating film is realized in a semiconductor device. To this end, a silicon oxide film and a silicon nitride film are formed on a substrate, which is then heated to a temperature within a range of 20° C.-600° C. so that a plasma nitridation process can be performed on the silicon nitride film. Further, a thermal process is performed in a non-oxide gas atmosphere. By performing these processes, the gate leakage current can be significantly reduced in the formed gate insulator, and the silicon oxide-equivalent thickness of the insulating film can be significantly decreased as well.Type: ApplicationFiled: January 27, 2003Publication date: December 18, 2003Applicant: FUJITSU LIMITEDInventor: Akihisa Yamaguchi
-
Patent number: 6510113Abstract: A recording apparatus, a recording method, and a recording medium, which allows a search operation based on a second segment information signal representing finely divided segments of a recording signal even in a player which can perform only a searching operation of a first segment information signal representing large segments of the recording signal. When a change of the second segment information signal of a signal to be recorded is detected, the first segment information signal being formed is updated and the first segment information signal is recorded together with an audio signal. That is, the second segment information signal of the signal to be recorded is converted into the first segment information signal and recorded together with the audio signal.Type: GrantFiled: October 18, 2000Date of Patent: January 21, 2003Assignee: Pioneer CorporationInventors: Akihisa Yamaguchi, Masaaki Matsumoto
-
Patent number: 6080373Abstract: Catalyst particles are contacted with a liquid and a gas in a vertically extending cylindrical vessel. The particles and liquid are placed in the vessel into which the gas and liquid are continuously fed from the bottom thereof so that an upwardly flowing mixture comprising the particles, liquid and gas is formed. The mixture is introduced into a gas separating zone disposed adjacent to an upper portion of the vessel to separate the mixture by gravity into a gas phase, a supernatant liquid phase and a phase rich in the catalyst particles. The gas and supernatant phases are continuously withdrawn from the separating zone while the catalyst particles-rich phase is continuously recycled to the bottom of the vessel by gravity.Type: GrantFiled: September 29, 1997Date of Patent: June 27, 2000Assignee: Chiyoda CorporationInventors: Fumihiko Uemura, Hideki Sugiyama, Chieko Nagasawa, Takeshi Minami, Kazuhiko Hamato, Noriyuki Yoneda, Akihisa Yamaguchi
-
Patent number: 6066762Abstract: A process for the production of a carbonyl compound such as acetic acid by reacting a carbonylatable compound such as methanol with a carbon monoxide in the presence of a carbonylation catalyst containing a noble metal complex supported on a porous, cross-linked vinylpyridine resin at a temperature of 140-250.degree. C., a carbon monoxide partial pressure of 7-30 kg/cm.sup.2 and a hydrogen partial pressure of 0.1-5 kg/cm.sup.2 to obtain a liquid product containing the carbonyl compound and an unreacted CO-containing gas product. The water content and the carbonylation degree of the liquid product within the reactor are maintained at 0.5-10% by weight and 0.5-0.9, respectively, The carbonyl compound is separated from the liquid product in a flasher and/or a distillation tower formed of titanium or a titanium-palladium alloy. The liquid product is introduced into a pressure reducing valve and then mixed with the CO-containing gas product before being fed to the flasher and/or distillation tower.Type: GrantFiled: December 23, 1997Date of Patent: May 23, 2000Assignee: Chiyoda CorporationInventors: Noriyuki Yoneda, Takeshi Minami, Yoshihiro Nakagawa, Ikuo Ohta, Akihisa Yamaguchi, Hideki Sugiyama, Fumihiko Uemura
-
Patent number: 5880311Abstract: Catalyst particles are contacted with a liquid and a gas in a vertically extending cylindrical vessel. The particles and liquid are placed in the vessel into which the gas and liquid are continuously fed from the bottom thereof so that an upwardly flowing mixture comprising the particles, liquid and gas is formed. The mixture is introduced into a gas separating zone disposed adjacent to an upper portion of the vessel to separate the mixture by gravity into a gas phase, a supernatant liquid phase and a phase rich in the catalyst particles. The gas and supernatant phases are continuously withdrawn from the separating zone while the catalyst particles-rich phase is continuously recycled to the bottom of the vessel by gravity.Type: GrantFiled: March 30, 1995Date of Patent: March 9, 1999Assignee: Tonen CorporationInventors: Fumihiko Uemura, Hideki Sugiyama, Chieko Nagasawa, Takeshi Minami, Kazuhiko Hamato, Noriyuki Yoneda, Akihisa Yamaguchi