Patents by Inventor Akihito Hamamatsu

Akihito Hamamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6646936
    Abstract: A DRAM includes a test mode circuit. Test mode circuit generates respective test mode signals of an L level and an H level by detecting first and second power supply voltages in response to first and second test mode shift signals, respectively. A control circuit controls peripheral circuits to input and output data for executing a special test to and from a plurality of memory cells in response to receiving of the test mode signals of an L level and an H level. Consequently, a semiconductor memory device can enter the test mode in a module.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: November 11, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akihito Hamamatsu, Shinji Tanaka
  • Publication number: 20030035328
    Abstract: A DRAM includes a test mode circuit. Test mode circuit generates respective test mode signals of an L level and an H level by detecting first and second power supply voltages in response to first and second test mode shift signals, respectively. A control circuit controls peripheral circuits to input and output data for executing a special test to and from a plurality of memory cells in response to receiving of the test mode signals of an L level and an H level. Consequently, a semiconductor memory device can enter the test mode in a module.
    Type: Application
    Filed: March 12, 2002
    Publication date: February 20, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akihito Hamamatsu, Shinji Tanaka